Overview on Latch-up Prevention in CMOS Integrated Circuits by Circuit Solutions

Ming Dou Ker, Zi Hong Jiang

Research output: Contribution to journalArticlepeer-review

Abstract

In CMOS chips, the wider layout rules were traditionally applied to overcome latch-up issues. However, the chip area with wider layout rules was often enlarged, and in turn the chip cost was also increased. To effectively improve latch-up immunity without enlarging the chip area, circuit methods were therefore invented. An overview on circuit methodology used to prevent latch-up issues in CMOS integrated circuits (ICs) is presented in this article. The circuit solutions, including reducing the I/O pad trigger current, sensing the trigger current to control the power supply, and restarting the power supply through an MOS switch to shut off the latch-up current, are overviewed.

Original languageEnglish
Pages (from-to)1
Number of pages1
JournalIEEE Journal of the Electron Devices Society
DOIs
StateAccepted/In press - 2022

Keywords

  • active guard ring
  • guard ring
  • Inverters
  • Junctions
  • latch-up
  • latch-up prevention
  • Layout
  • Logic gates
  • over-current detector
  • Power supplies
  • Sensors
  • silicon-controlled rectifier (SCR)
  • Transistors
  • voltage regulator

Fingerprint

Dive into the research topics of 'Overview on Latch-up Prevention in CMOS Integrated Circuits by Circuit Solutions'. Together they form a unique fingerprint.

Cite this