Overview on ESD protection designs of low-parasitic capacitance for RF ICs in CMOS technologies

Ming-Dou Ker*, Chun Yu Lin, Yuan Wen Hsiao

*Corresponding author for this work

    Research output: Contribution to journalReview articlepeer-review

    54 Scopus citations

    Abstract

    CMOS technology has been widely used to implement radio-frequency integrated circuits (RF ICs). However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of RF ICs. Therefore, on-chip ESD protection designs must be added at all input/output pads in RF circuits against ESD damages. To minimize the impacts from ESD protection circuit on RF performances, ESD protection circuit at input/output pads must be carefully designed. An overview on ESD protection designs with low parasitic capacitance for RF circuits in CMOS technology is presented in this paper. The comparisons among these ESD protection designs are also discussed. With the reduced parasitic capacitance, ESD protection circuit can be easily combined or co-designed with RF circuits. As the operating frequencies of RF circuits increase, on-chip ESD protection designs for RF applications will continuously be an important design task.

    Original languageEnglish
    Article number5688227
    Pages (from-to)207-218
    Number of pages12
    JournalIEEE Transactions on Device and Materials Reliability
    Volume11
    Issue number2
    DOIs
    StatePublished - 1 Jun 2011

    Keywords

    • Electrostatic discharge (ESD)
    • ESD protection circuits
    • low capacitance
    • radio-frequency integrated circuit (RF IC)

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