Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology

Physics & Astronomy

• clamps 77%
• rails 75%
• low voltage 62%
• CMOS 57%
• high voltages 55%
• electrostatics 48%
• oxides 39%
• electric potential 34%
• circuit protection 17%
• systems-on-a-chip 15%
• leakage 8%
• transistors 8%
• chips 8%

Engineering & Materials Science

• Electrostatic discharge 83%
• Clamping devices 71%
• Oxides 54%
• Rails 54%
• Networks (circuits) 35%
• Electric potential 32%
• Leakage currents 11%
• Transistors 9%

Chemical Compounds

• Electrostatic Discharge 100%
• Leakage Current 14%