TY - JOUR
T1 - Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces
T2 - Design concept and circuit implementations
AU - Ker, Ming-Dou
AU - Lin, Kun Hsien
PY - 2006/12/1
Y1 - 2006/12/1
N2 - Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O. interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.
AB - Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O. interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.
KW - ESD protection design
KW - Electrostatic discharge (ESD)
KW - Gate-oxide reliability
KW - High-voltage tolerant
KW - Mixed-voltage I/o interfaces
KW - Power-rail ESD clamp circuit
UR - http://www.scopus.com/inward/record.url?scp=33947098957&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2005.856040
DO - 10.1109/TCSI.2005.856040
M3 - Article
AN - SCOPUS:33947098957
SN - 1549-8328
VL - 53
SP - 235
EP - 246
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 2
ER -