Outlier Detection for Analog Tests Using Deep Learning Techniques

Chin Kuan Lin, Cheng Che Lu, Shuo Wen Chang, Ying Hua Chu, Kai Chiang Wu, Mango Chia Tso Chao

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations


With the increasing demand for high reliability of products, how to prevent potential defective devices from shipping to customers is a serious issue about which more and more companies are concerned. Toward this end, many test methods have been developed to screen out outliers. However, basic statistical paradigm may not be enough to handle the shrinking transistor size and increasingly complex circuit design. In this paper, we propose to use the concept of Z-score derived from our proposed neural network, called single density network (SDN), to define level of abnormality. We also define new metrics called self-excluded fail rate (SE fail rate) and normalized area under curve (AUC) to be our criteria to quantify and further visualize the outcome. To filter out spatially-correlated outliers, we make use of specific information of neighboring dice and encode them into our input features for the proposed SDN. A series of experimental results on industrial data reveal the effectiveness of our methodology and the better ability to identify defective outliers than existing conventional statistical approaches for a variety of analog tests.

Original languageEnglish
Title of host publicationProceedings - 2023 IEEE 41st VLSI Test Symposium, VTS 2023
PublisherIEEE Computer Society
ISBN (Electronic)9798350346305
StatePublished - 2023
Event41st IEEE VLSI Test Symposium, VTS 2023 - San Diego, United States
Duration: 24 Apr 202326 Apr 2023

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference41st IEEE VLSI Test Symposium, VTS 2023
Country/TerritoryUnited States
CitySan Diego


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