Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design

Jen Chieh Liu; Tzu Yun Wu; Tuo-Hung Hou

doi:10.1109/TCSII.2018.2821268

Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design

Jen Chieh Liu, Tzu Yun Wu, Tuo-Hung Hou^*

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

6 Scopus citations

Abstract

A device-circuit co-design strategy of incremental step pulse programming (ISPP) tailored specifically for resistive-switching random access memory (RRAM) is elaborated using HfO₂ RRAM as an example. The proposed strategy optimizes ISPP by considering programming energy, speed, peripheral circuit design, and device lifetime simultaneously. Interplay between ISPP configuration and device switching behavior is comprehensively clarified, and the result provides useful indicators for estimating peripheral circuit overhead and programming performance. Overstress effects affect both switching voltages and endurance lifetime substantially and, thus, should be carefully minimized.

Original language	English
Pages (from-to)	617-621
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	65
Issue number	5
DOIs	https://doi.org/10.1109/TCSII.2018.2821268
State	Published - 1 May 2018

Keywords

device-circuit co-design
ISPP
over stress
RRAM

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10.1109/TCSII.2018.2821268

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title = "Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design",

abstract = "A device-circuit co-design strategy of incremental step pulse programming (ISPP) tailored specifically for resistive-switching random access memory (RRAM) is elaborated using HfO2 RRAM as an example. The proposed strategy optimizes ISPP by considering programming energy, speed, peripheral circuit design, and device lifetime simultaneously. Interplay between ISPP configuration and device switching behavior is comprehensively clarified, and the result provides useful indicators for estimating peripheral circuit overhead and programming performance. Overstress effects affect both switching voltages and endurance lifetime substantially and, thus, should be carefully minimized.",

keywords = "device-circuit co-design, ISPP, over stress, RRAM",

author = "Liu, {Jen Chieh} and Wu, {Tzu Yun} and Tuo-Hung Hou",

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N2 - A device-circuit co-design strategy of incremental step pulse programming (ISPP) tailored specifically for resistive-switching random access memory (RRAM) is elaborated using HfO2 RRAM as an example. The proposed strategy optimizes ISPP by considering programming energy, speed, peripheral circuit design, and device lifetime simultaneously. Interplay between ISPP configuration and device switching behavior is comprehensively clarified, and the result provides useful indicators for estimating peripheral circuit overhead and programming performance. Overstress effects affect both switching voltages and endurance lifetime substantially and, thus, should be carefully minimized.

AB - A device-circuit co-design strategy of incremental step pulse programming (ISPP) tailored specifically for resistive-switching random access memory (RRAM) is elaborated using HfO2 RRAM as an example. The proposed strategy optimizes ISPP by considering programming energy, speed, peripheral circuit design, and device lifetime simultaneously. Interplay between ISPP configuration and device switching behavior is comprehensively clarified, and the result provides useful indicators for estimating peripheral circuit overhead and programming performance. Overstress effects affect both switching voltages and endurance lifetime substantially and, thus, should be carefully minimized.

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Optimizing Incremental Step Pulse Programming for RRAM Through Device-Circuit Co-Design

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Keywords

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