Optimized layout on ESD protection diode with low parasitic capacitance

Chih Ting Yeh; Ming-Dou Ker

doi:10.1109/ICSICT.2010.5667306

Optimized layout on ESD protection diode with low parasitic capacitance

Chih Ting Yeh^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at GHz RF and high-speed I/O pads in CMOS integrated circuits (ICs) due to the small parasitic loading effect and high ESD robustness. Based on waffle layout style, two modified layout styles have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the figures of merit (FOMs) of ESD protection diodes with new proposed layout styles can be successfully improved.

Original language	English
Title of host publication	ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Pages	1701-1703
Number of pages	3
DOIs	https://doi.org/10.1109/ICSICT.2010.5667306
State	Published - 1 Dec 2010
Event	2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China Duration: 1 Nov 2010 → 4 Nov 2010

Publication series

Name	ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Conference

Conference	2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
Country/Territory	China
City	Shanghai
Period	1/11/10 → 4/11/10

Access to Document

10.1109/ICSICT.2010.5667306

Cite this

Yeh, C. T., & Ker, M.-D. (2010). Optimized layout on ESD protection diode with low parasitic capacitance. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 1701-1703). Article 5667306 (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2010.5667306

@inproceedings{13f2dd44f8544ecca47ce34c517c6b1b,

title = "Optimized layout on ESD protection diode with low parasitic capacitance",

abstract = "The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at GHz RF and high-speed I/O pads in CMOS integrated circuits (ICs) due to the small parasitic loading effect and high ESD robustness. Based on waffle layout style, two modified layout styles have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the figures of merit (FOMs) of ESD protection diodes with new proposed layout styles can be successfully improved.",

author = "Yeh, {Chih Ting} and Ming-Dou Ker",

year = "2010",

month = dec,

day = "1",

doi = "10.1109/ICSICT.2010.5667306",

language = "English",

isbn = "9781424457984",

series = "ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

pages = "1701--1703",

booktitle = "ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

note = "2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology ; Conference date: 01-11-2010 Through 04-11-2010",

}

Yeh, CT & Ker, M-D 2010, Optimized layout on ESD protection diode with low parasitic capacitance. in ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 5667306, ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings, pp. 1701-1703, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 1/11/10. https://doi.org/10.1109/ICSICT.2010.5667306

Optimized layout on ESD protection diode with low parasitic capacitance. / Yeh, Chih Ting; Ker, Ming-Dou.
ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. p. 1701-1703 5667306 (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Optimized layout on ESD protection diode with low parasitic capacitance

AU - Yeh, Chih Ting

AU - Ker, Ming-Dou

PY - 2010/12/1

Y1 - 2010/12/1

N2 - The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at GHz RF and high-speed I/O pads in CMOS integrated circuits (ICs) due to the small parasitic loading effect and high ESD robustness. Based on waffle layout style, two modified layout styles have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the figures of merit (FOMs) of ESD protection diodes with new proposed layout styles can be successfully improved.

AB - The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at GHz RF and high-speed I/O pads in CMOS integrated circuits (ICs) due to the small parasitic loading effect and high ESD robustness. Based on waffle layout style, two modified layout styles have been proposed, which are called as multi-waffle and multi-waffle-hollow layout styles. Experimental results in a 90-nm CMOS process have confirmed that the figures of merit (FOMs) of ESD protection diodes with new proposed layout styles can be successfully improved.

UR - http://www.scopus.com/inward/record.url?scp=78751486894&partnerID=8YFLogxK

U2 - 10.1109/ICSICT.2010.5667306

DO - 10.1109/ICSICT.2010.5667306

M3 - Conference contribution

AN - SCOPUS:78751486894

SN - 9781424457984

T3 - ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

SP - 1701

EP - 1703

BT - ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

T2 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

Y2 - 1 November 2010 through 4 November 2010

ER -

Yeh CT, Ker MD. Optimized layout on ESD protection diode with low parasitic capacitance. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. p. 1701-1703. 5667306. (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings). doi: 10.1109/ICSICT.2010.5667306

Optimized layout on ESD protection diode with low parasitic capacitance

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this