Optimization on On-Chip Surge Protection Device for USB Type-C HV Pins

Ming Chun Chen, Ming Dou Ker, Yeh Ning Jou, Jian Hsing Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

On-chip surge protection device for VBUS pins in the USB type-C interfaces is studied. Comparing to the conventional PNP BJT device, the proposed PNP BJT can effectively boost its immunity against surge and ESD stresses. Silicon chip fabricated in a 0.15-μm BCD technology has been measured to successfully verify the surge immunity of the proposed PNP BJT.

Original languageEnglish
Title of host publication2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728161693
DOIs
StatePublished - 20 Jul 2020
Event2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2020 - Singapore, Singapore
Duration: 20 Jul 202023 Jul 2020

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume2020-July

Conference

Conference2020 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2020
Country/TerritorySingapore
CitySingapore
Period20/07/2023/07/20

Keywords

  • PNP BJT
  • Surge protection device
  • USB type-C

Fingerprint

Dive into the research topics of 'Optimization on On-Chip Surge Protection Device for USB Type-C HV Pins'. Together they form a unique fingerprint.

Cite this