Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology

Shin Hung Chen*, Ming-Dou Ker

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    8 Scopus citations

    Abstract

    NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection ability. All of them are based on a similar circuit scheme with 3-stage inverters to drive the ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage-inverter and 1-stage-inverter controlling circuits have been studied to verify the optimal circuit schemes in NMOS-based power-rail ESD clamp circuits.

    Original languageEnglish
    Title of host publicationProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
    Pages666-669
    Number of pages4
    DOIs
    StatePublished - 2008
    Event15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's, Malta
    Duration: 31 Aug 20083 Sep 2008

    Publication series

    NameProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

    Conference

    Conference15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
    Country/TerritoryMalta
    CitySt. Julian's
    Period31/08/083/09/08

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