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Optimization on MOS-triggered SCR structures for On-Chip ESD protection
Shih Hung Chen
*
,
Ming-Dou Ker
*
Corresponding author for this work
Research output
:
Contribution to journal
›
Article
›
peer-review
18
Scopus citations
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Dive into the research topics of 'Optimization on MOS-triggered SCR structures for On-Chip ESD protection'. Together they form a unique fingerprint.
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Keyphrases
On chip
100%
Electrostatic Discharge (ESD) Protection
100%
Silicon-controlled Rectifier
100%
MOS Transistor
50%
CMOS Technology
16%
Channel Length
16%
Electrostatic Discharge
16%
Trigger Voltage
16%
Deep Submicron
16%
Current Distribution
16%
Trigger Mechanism
16%
Advanced CMOS
16%
Holding Voltage
16%
Trigger Current
16%
Voltage Holding
16%
Second Breakdown Current
16%
Current Discharge
16%
Engineering
Electrostatic Discharge
100%
Silicon-Controlled Rectifier
100%
Channel Length
16%
Current Distribution
16%
Holding Voltage
16%
Computer Science
Trigger Voltage
100%
Holding Voltage
100%
Material Science
Silicon
100%
Transistor
50%
Earth and Planetary Sciences
Silicon Controlled Rectifier
100%
Trigger Mechanism
16%