Optimization on layout style of diode stackup for on-chip ESD protection

Chun Yu Lin; Mei Lian Fan

doi:10.1109/TDMR.2014.2311130

Optimization on layout style of diode stackup for on-chip ESD protection

Chun Yu Lin, Mei Lian Fan

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than V_DD or lower than V_SS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.

Original language	English
Article number	6763105
Pages (from-to)	775-777
Number of pages	3
Journal	IEEE Transactions on Device and Materials Reliability
Volume	14
Issue number	2
DOIs	https://doi.org/10.1109/TDMR.2014.2311130
State	Published - Jun 2014

Keywords

Diode
electrostatic discharge (ESD)
layout
stackup

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10.1109/TDMR.2014.2311130

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abstract = "The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than VDD or lower than VSS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.",

keywords = "Diode, electrostatic discharge (ESD), layout, stackup",

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AB - The diode stackup has been used as on-chip electrostatic discharge (ESD) protection for some applications in which the input/output signal swing is higher than VDD or lower than VSS. A novel ESD protection structure of diode stackup is proposed for effective on-chip ESD protection. Experimental results in 65-nm CMOS process show that the optimization on layout style can improve the ESD robustness, decrease the turn-on resistance, and lessen the parasitic capacitance of the diode stackup.

KW - Diode

KW - electrostatic discharge (ESD)

KW - layout

KW - stackup

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Optimization on layout style of diode stackup for on-chip ESD protection

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Keywords

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