Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology

Shin Hung Chen; Ming-Dou Ker

doi:10.1109/IPFA.2007.4378093

Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology

Shin Hung Chen^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

4 Scopus citations

Abstract

PMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, tumed-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the PMOS-triggered SCR device. The channel lengths of the embedded PMOS transistors in the PMOS-triggered SCR devices should be optimized to achieve the most efficient ESD protection design in deep-submicron or nanoscale CMOS technology.

Original language	English
Title of host publication	Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007
Pages	245-248
Number of pages	4
DOIs	https://doi.org/10.1109/IPFA.2007.4378093
State	Published - 1 Dec 2007
Event	2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits - Bangalore, India Duration: 11 Jul 2007 → 13 Jul 2007

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Conference

Conference	2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits
Country/Territory	India
City	Bangalore
Period	11/07/07 → 13/07/07

Access to Document

10.1109/IPFA.2007.4378093

Cite this

Chen, S. H., & Ker, M.-D. (2007). Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology. In Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007 (pp. 245-248). Article 4378093 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). https://doi.org/10.1109/IPFA.2007.4378093

Chen, Shin Hung ; Ker, Ming-Dou. / Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology. Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007. 2007. pp. 245-248 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

@inproceedings{19b30b0876d34a33aac19e3e43887dfd,

title = "Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology",

abstract = "PMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, tumed-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the PMOS-triggered SCR device. The channel lengths of the embedded PMOS transistors in the PMOS-triggered SCR devices should be optimized to achieve the most efficient ESD protection design in deep-submicron or nanoscale CMOS technology.",

author = "Chen, {Shin Hung} and Ming-Dou Ker",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/IPFA.2007.4378093",

language = "English",

isbn = "1424410142",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

pages = "245--248",

booktitle = "Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007",

note = "2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits ; Conference date: 11-07-2007 Through 13-07-2007",

}

Chen, SH & Ker, M-D 2007, Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology. in Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007., 4378093, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, pp. 245-248, 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, Bangalore, India, 11/07/07. https://doi.org/10.1109/IPFA.2007.4378093

Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology. / Chen, Shin Hung; Ker, Ming-Dou.
Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007. 2007. p. 245-248 4378093 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology

AU - Chen, Shin Hung

AU - Ker, Ming-Dou

PY - 2007/12/1

Y1 - 2007/12/1

N2 - PMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, tumed-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the PMOS-triggered SCR device. The channel lengths of the embedded PMOS transistors in the PMOS-triggered SCR devices should be optimized to achieve the most efficient ESD protection design in deep-submicron or nanoscale CMOS technology.

AB - PMOS-triggered SCR devices with initial-on function have been proposed to achieve an efficient ESD protection in deep-submicron CMOS technology. The channel length of the embedded PMOS transistor in the PMOS-triggered SCR device dominates the trigger mechanism to govern the trigger voltage, holding voltage, tumed-on resistance, second breakdown current, turn-on efficiency, and ESD robustness of the PMOS-triggered SCR device. The channel lengths of the embedded PMOS transistors in the PMOS-triggered SCR devices should be optimized to achieve the most efficient ESD protection design in deep-submicron or nanoscale CMOS technology.

UR - http://www.scopus.com/inward/record.url?scp=39749190739&partnerID=8YFLogxK

U2 - 10.1109/IPFA.2007.4378093

DO - 10.1109/IPFA.2007.4378093

M3 - Conference contribution

AN - SCOPUS:39749190739

SN - 1424410142

SN - 9781424410149

T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

SP - 245

EP - 248

BT - Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007

T2 - 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits

Y2 - 11 July 2007 through 13 July 2007

ER -

Chen SH, Ker MD. Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology. In Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007. 2007. p. 245-248. 4378093. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2007.4378093

Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this