Optimization Design on Active Guard Ring to Improve Latch-Up Immunity of CMOS Integrated Circuits

Keyphrases

• Latch-up 100%
• CMOS Integrated Circuits 100%
• Design Optimization 100%
• Guard Ring 100%
• Input-output 83%
• Electrostatic Discharge (ESD) Protection 33%
• Trigger Current 33%
• On chip 16%
• NMOS 16%
• CMOS Technology 16%
• Undershoot 16%
• MOSFET 16%
• Proposed Design 16%
• Electrostatic Discharge 16%
• PMOS 16%
• Power Rail 16%
• Output Device 16%
• Protection Device 16%

Engineering

• Electrostatic Discharge 100%
• CMOS Integrated Circuits 100%
• Design Optimization 100%
• Active Guard 100%
• Internals 66%
• Metal-Oxide-Semiconductor Field-Effect Transistor 33%
• Power Rail 33%
• Protection Device 33%