ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design

Samuel Liu; Jen Ho Kuo; Luba Tang; Ning Chi Huang; Der Yu Tsai; M. H. Yang; Kai Chiang Wu

doi:10.1109/VLSI-DAT52063.2021.9427328

ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design

Samuel Liu, Jen Ho Kuo, Luba Tang, Ning Chi Huang, Der Yu Tsai, M. H. Yang, Kai Chiang Wu

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The calculation of the convolution is considered the most important part in convolutional neural network-based artificial intelligence (AI) deep learning accelerator (DLA) architecture. Regardless of employing the traditional von Neumann architecture or the non-von Neumann compute-in-memory architecture, the variations arising from the integrated circuit (IC) process at the mass production stage must be considered. The AI model accuracy also needs to be improved. The open neural network compiler (ONNC) is an architecture-aware AI software development kit toolchain, which is capable of evaluating the AI model on fixed-point Edge AI DLAs for the open neural network exchange model. In this paper, the ONNC toolchain and the NVIDIA DLA (NVDLA) field-programmable gate array are employed to investigate the NVDLA static random-access memory stuck-at fault impact on model accuracy. The fault-mitigating results after applying a recovery mechanism in the IC process hard failure are also discussed.A method for utilizing the ONNC framework and the recovery guidelines for the resistive random-access memory -based computer-integrated manufacturing DLA architecture is also proposed.

Original language	English
Title of host publication	2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665419154
DOIs	https://doi.org/10.1109/VLSI-DAT52063.2021.9427328
State	Published - 19 Apr 2021
Event	2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Hsinchu, Taiwan Duration: 19 Apr 2021 → 22 Apr 2021

Publication series

Name	2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings

Conference

Conference	2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021
Country/Territory	Taiwan
City	Hsinchu
Period	19/04/21 → 22/04/21

Keywords

CIM Simulator
Compilers
Deep Learning Accelerators
Fault-Mitigating Mechanisms
NVDLA
ONNC
ReRAM
SRAM Stuck-at Fault

Access to Document

10.1109/VLSI-DAT52063.2021.9427328

Cite this

Liu, S., Kuo, J. H., Tang, L., Huang, N. C., Tsai, D. Y., Yang, M. H., & Wu, K. C. (2021). ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design. In 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings Article 9427328 (2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-DAT52063.2021.9427328

Liu, Samuel ; Kuo, Jen Ho ; Tang, Luba et al. / ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design. 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. (2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings).

@inproceedings{9a5b7cb789cd4bd1a38a5fc309249a41,

title = "ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design",

abstract = "The calculation of the convolution is considered the most important part in convolutional neural network-based artificial intelligence (AI) deep learning accelerator (DLA) architecture. Regardless of employing the traditional von Neumann architecture or the non-von Neumann compute-in-memory architecture, the variations arising from the integrated circuit (IC) process at the mass production stage must be considered. The AI model accuracy also needs to be improved. The open neural network compiler (ONNC) is an architecture-aware AI software development kit toolchain, which is capable of evaluating the AI model on fixed-point Edge AI DLAs for the open neural network exchange model. In this paper, the ONNC toolchain and the NVIDIA DLA (NVDLA) field-programmable gate array are employed to investigate the NVDLA static random-access memory stuck-at fault impact on model accuracy. The fault-mitigating results after applying a recovery mechanism in the IC process hard failure are also discussed.A method for utilizing the ONNC framework and the recovery guidelines for the resistive random-access memory -based computer-integrated manufacturing DLA architecture is also proposed. ",

keywords = "CIM Simulator, Compilers, Deep Learning Accelerators, Fault-Mitigating Mechanisms, NVDLA, ONNC, ReRAM, SRAM Stuck-at Fault",

author = "Samuel Liu and Kuo, {Jen Ho} and Luba Tang and Huang, {Ning Chi} and Tsai, {Der Yu} and Yang, {M. H.} and Wu, {Kai Chiang}",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 ; Conference date: 19-04-2021 Through 22-04-2021",

year = "2021",

month = apr,

day = "19",

doi = "10.1109/VLSI-DAT52063.2021.9427328",

language = "English",

series = "2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings",

address = "美國",

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Liu, S, Kuo, JH, Tang, L, Huang, NC, Tsai, DY, Yang, MH & Wu, KC 2021, ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design. in 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings., 9427328, 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021, Hsinchu, Taiwan, 19/04/21. https://doi.org/10.1109/VLSI-DAT52063.2021.9427328

ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design. / Liu, Samuel; Kuo, Jen Ho; Tang, Luba et al.
2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2021. 9427328 (2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design

AU - Liu, Samuel

AU - Kuo, Jen Ho

AU - Tang, Luba

AU - Huang, Ning Chi

AU - Tsai, Der Yu

AU - Yang, M. H.

AU - Wu, Kai Chiang

PY - 2021/4/19

Y1 - 2021/4/19

N2 - The calculation of the convolution is considered the most important part in convolutional neural network-based artificial intelligence (AI) deep learning accelerator (DLA) architecture. Regardless of employing the traditional von Neumann architecture or the non-von Neumann compute-in-memory architecture, the variations arising from the integrated circuit (IC) process at the mass production stage must be considered. The AI model accuracy also needs to be improved. The open neural network compiler (ONNC) is an architecture-aware AI software development kit toolchain, which is capable of evaluating the AI model on fixed-point Edge AI DLAs for the open neural network exchange model. In this paper, the ONNC toolchain and the NVIDIA DLA (NVDLA) field-programmable gate array are employed to investigate the NVDLA static random-access memory stuck-at fault impact on model accuracy. The fault-mitigating results after applying a recovery mechanism in the IC process hard failure are also discussed.A method for utilizing the ONNC framework and the recovery guidelines for the resistive random-access memory -based computer-integrated manufacturing DLA architecture is also proposed.

AB - The calculation of the convolution is considered the most important part in convolutional neural network-based artificial intelligence (AI) deep learning accelerator (DLA) architecture. Regardless of employing the traditional von Neumann architecture or the non-von Neumann compute-in-memory architecture, the variations arising from the integrated circuit (IC) process at the mass production stage must be considered. The AI model accuracy also needs to be improved. The open neural network compiler (ONNC) is an architecture-aware AI software development kit toolchain, which is capable of evaluating the AI model on fixed-point Edge AI DLAs for the open neural network exchange model. In this paper, the ONNC toolchain and the NVIDIA DLA (NVDLA) field-programmable gate array are employed to investigate the NVDLA static random-access memory stuck-at fault impact on model accuracy. The fault-mitigating results after applying a recovery mechanism in the IC process hard failure are also discussed.A method for utilizing the ONNC framework and the recovery guidelines for the resistive random-access memory -based computer-integrated manufacturing DLA architecture is also proposed.

KW - CIM Simulator

KW - Compilers

KW - Deep Learning Accelerators

KW - Fault-Mitigating Mechanisms

KW - NVDLA

KW - ONNC

KW - ReRAM

KW - SRAM Stuck-at Fault

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U2 - 10.1109/VLSI-DAT52063.2021.9427328

DO - 10.1109/VLSI-DAT52063.2021.9427328

M3 - Conference contribution

AN - SCOPUS:85106591457

T3 - 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings

BT - 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021

Y2 - 19 April 2021 through 22 April 2021

ER -

Liu S, Kuo JH, Tang L, Huang NC, Tsai DY, Yang MH et al. ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design. In 2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2021. 9427328. (2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings). doi: 10.1109/VLSI-DAT52063.2021.9427328

ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design

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