Onboard FPGA-based SAR processing for future spaceborne systems

Charles Le*, Samuel Chan, Frank Cheng, Winston Fang, Mark Fischman, Scott Hensley, Robert Johnson, Michael Jourdan, Miguel Marina, Bruce Parham, Francois Rogez, Paul Rosen, Biren Shah, Stephanie Taft

*Corresponding author for this work

Research output: Contribution to conferencePaperpeer-review

44 Scopus citations


We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.

Original languageEnglish
Number of pages6
StatePublished - Apr 2004
EventProceedings of the IEEE Radar Conference - Philadelphia, PA, United States
Duration: 26 Apr 200429 Apr 2004


ConferenceProceedings of the IEEE Radar Conference
Country/TerritoryUnited States
CityPhiladelphia, PA


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