Onboard FPGA-based SAR processing for future spaceborne systems

Charles Le; Samuel Chan; Frank Cheng; Winston Fang; Mark Fischman; Scott Hensley; Robert Johnson; Michael Jourdan; Miguel Marina; Bruce Parham; Francois Rogez; Paul Rosen; Biren Shah; Stephanie Taft

doi:10.1109/NRC.2004.1316388

Onboard FPGA-based SAR processing for future spaceborne systems

Charles Le^*, Samuel Chan, Frank Cheng, Winston Fang, Mark Fischman, Scott Hensley, Robert Johnson, Michael Jourdan, Miguel Marina, Bruce Parham, Francois Rogez, Paul Rosen, Biren Shah, Stephanie Taft

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to conference › Paper › peer-review

48 Scopus citations

Abstract

We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.

Original language	English
Pages	15-20
Number of pages	6
DOIs	https://doi.org/10.1109/NRC.2004.1316388
State	Published - Apr 2004
Event	Proceedings of the IEEE Radar Conference - Philadelphia, PA, United States Duration: 26 Apr 2004 → 29 Apr 2004

Conference

Conference	Proceedings of the IEEE Radar Conference
Country/Territory	United States
City	Philadelphia, PA
Period	26/04/04 → 29/04/04

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10.1109/NRC.2004.1316388

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Le, C., Chan, S., Cheng, F., Fang, W., Fischman, M., Hensley, S., Johnson, R., Jourdan, M., Marina, M., Parham, B., Rogez, F., Rosen, P., Shah, B., & Taft, S. (2004). Onboard FPGA-based SAR processing for future spaceborne systems. 15-20. Paper presented at Proceedings of the IEEE Radar Conference, Philadelphia, PA, United States. https://doi.org/10.1109/NRC.2004.1316388

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title = "Onboard FPGA-based SAR processing for future spaceborne systems",

abstract = "We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.",

author = "Charles Le and Samuel Chan and Frank Cheng and Winston Fang and Mark Fischman and Scott Hensley and Robert Johnson and Michael Jourdan and Miguel Marina and Bruce Parham and Francois Rogez and Paul Rosen and Biren Shah and Stephanie Taft",

year = "2004",

month = apr,

doi = "10.1109/NRC.2004.1316388",

language = "English",

pages = "15--20",

note = "Proceedings of the IEEE Radar Conference ; Conference date: 26-04-2004 Through 29-04-2004",

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Le, C, Chan, S, Cheng, F, Fang, W, Fischman, M, Hensley, S, Johnson, R, Jourdan, M, Marina, M, Parham, B, Rogez, F, Rosen, P, Shah, B & Taft, S 2004, 'Onboard FPGA-based SAR processing for future spaceborne systems', Paper presented at Proceedings of the IEEE Radar Conference, Philadelphia, PA, United States, 26/04/04 - 29/04/04 pp. 15-20. https://doi.org/10.1109/NRC.2004.1316388

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AU - Le, Charles

AU - Chan, Samuel

AU - Cheng, Frank

AU - Fang, Winston

AU - Fischman, Mark

AU - Hensley, Scott

AU - Johnson, Robert

AU - Jourdan, Michael

AU - Marina, Miguel

AU - Parham, Bruce

AU - Rogez, Francois

AU - Rosen, Paul

AU - Shah, Biren

AU - Taft, Stephanie

PY - 2004/4

Y1 - 2004/4

N2 - We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.

AB - We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.

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U2 - 10.1109/NRC.2004.1316388

DO - 10.1109/NRC.2004.1316388

M3 - Paper

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SP - 15

EP - 20

T2 - Proceedings of the IEEE Radar Conference

Y2 - 26 April 2004 through 29 April 2004

ER -

Onboard FPGA-based SAR processing for future spaceborne systems

Abstract

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