We present a real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images in future spaceborne system. In particular, we will discuss the integrated design approach, from top-level algorithm specifications and system requirements, design methodology, functional verification and performance validation, down to hardware design and implementation.
|Number of pages||6|
|State||Published - Apr 2004|
|Event||Proceedings of the IEEE Radar Conference - Philadelphia, PA, United States|
Duration: 26 Apr 2004 → 29 Apr 2004
|Conference||Proceedings of the IEEE Radar Conference|
|Period||26/04/04 → 29/04/04|