On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

Ming-Dou Ker; Po Yen Chiu; Fu Yi Tsai; Yeong Jar Chang

doi:10.1109/ISCAS.2009.5118254

On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

Ming-Dou Ker^*, Po Yen Chiu, Fu Yi Tsai, Yeong Jar Chang

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

15 Scopus citations

Abstract

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25°C in the silicon chip. Moreover, it can achieve ESD robustness of over 8kV in human-body-model (HBM) and 750V in machine-model (MM) ESD tests, respectively.

Original language	English
Title of host publication	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Pages	2281-2284
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2009.5118254
State	Published - 2009
Event	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 - Taipei, Taiwan Duration: 24 May 2009 → 27 May 2009

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009
Country/Territory	Taiwan
City	Taipei
Period	24/05/09 → 27/05/09

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10.1109/ISCAS.2009.5118254

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Ker, M.-D., Chiu, P. Y., Tsai, F. Y., & Chang, Y. J. (2009). On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process. In 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 (pp. 2281-2284). Article 5118254 (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2009.5118254

@inproceedings{99cbaed597a646679b0cea719a0586f8,

title = "On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process",

abstract = "A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25°C in the silicon chip. Moreover, it can achieve ESD robustness of over 8kV in human-body-model (HBM) and 750V in machine-model (MM) ESD tests, respectively.",

author = "Ming-Dou Ker and Chiu, {Po Yen} and Tsai, {Fu Yi} and Chang, {Yeong Jar}",

year = "2009",

doi = "10.1109/ISCAS.2009.5118254",

language = "English",

isbn = "9781424438280",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "2281--2284",

booktitle = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009",

note = "2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009 ; Conference date: 24-05-2009 Through 27-05-2009",

}

Ker, M-D, Chiu, PY, Tsai, FY & Chang, YJ 2009, On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process. in 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009., 5118254, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 2281-2284, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009, Taipei, Taiwan, 24/05/09. https://doi.org/10.1109/ISCAS.2009.5118254

On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process. / Ker, Ming-Dou; Chiu, Po Yen; Tsai, Fu Yi et al.
2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. 2009. p. 2281-2284 5118254 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Chiu, Po Yen

AU - Tsai, Fu Yi

AU - Chang, Yeong Jar

PY - 2009

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N2 - A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25°C in the silicon chip. Moreover, it can achieve ESD robustness of over 8kV in human-body-model (HBM) and 750V in machine-model (MM) ESD tests, respectively.

AB - A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with the consideration of gate-leakage issue is proposed and verified in a 65-nm low-voltage CMOS process. The new proposed design has a very small leakage current of only 228 nA at 25°C in the silicon chip. Moreover, it can achieve ESD robustness of over 8kV in human-body-model (HBM) and 750V in machine-model (MM) ESD tests, respectively.

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DO - 10.1109/ISCAS.2009.5118254

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SN - 9781424438280

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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BT - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009

T2 - 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009

Y2 - 24 May 2009 through 27 May 2009

ER -

On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

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