On the automatic HDL bug identification

Ming Chih Lai; Yih-Lang Li; Shyan-Ming Yuan

doi:10.1080/09720529.2005.10698049

On the automatic HDL bug identification

Ming Chih Lai^*, Yih-Lang Li, Shyan-Ming Yuan

^*Corresponding author for this work

Department of Computer Science

Research output: Contribution to journal › Article › peer-review

Abstract

The debugging is the design gap bottleneck of today’s complex HDL (Hardware Description Language) design. Base on the design and simulation dumping, this paper proposes an automatic bug diagnosis method. By analyzing the difference between the output signals wave forms of HDL design and the design 10 timing specification, each HDL statement is given a weight indicating the degree of probability of a bug. The experiments show that our approach can identify a bug with 89% accuracy.

Original language	English
Pages (from-to)	413-425
Number of pages	13
Journal	Journal of Discrete Mathematical Sciences and Cryptography
Volume	8
Issue number	3
DOIs	https://doi.org/10.1080/09720529.2005.10698049
State	Published - 1 Jan 2005

Keywords

Asic design
Debug
HDL
Inference synthesis
Reasoning
Simulation
Verification

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10.1080/09720529.2005.10698049

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AB - The debugging is the design gap bottleneck of today’s complex HDL (Hardware Description Language) design. Base on the design and simulation dumping, this paper proposes an automatic bug diagnosis method. By analyzing the difference between the output signals wave forms of HDL design and the design 10 timing specification, each HDL statement is given a weight indicating the degree of probability of a bug. The experiments show that our approach can identify a bug with 89% accuracy.

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KW - Debug

KW - HDL

KW - Inference synthesis

KW - Reasoning

KW - Simulation

KW - Verification

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On the automatic HDL bug identification

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Keywords

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