Skip to main navigation
Skip to search
Skip to main content
National Yang Ming Chiao Tung University Academic Hub Home
English
中文
Search content at National Yang Ming Chiao Tung University Academic Hub
Home
Profiles
Research units
Research output
Projects
Prizes
Activities
Equipment
Impacts
On Reducing LDE Variations in Modern Analog Placement
Thasreefa AK
, Abhishek Patyal
, Hao Yu Chi
,
Po Hung Lin
,
Hung Ming Chen
Institute of Intelligent Systems
Institute of Electronics
Research output
:
Contribution to journal
›
Article
›
peer-review
2
Scopus citations
Overview
Fingerprint
Fingerprint
Dive into the research topics of 'On Reducing LDE Variations in Modern Analog Placement'. Together they form a unique fingerprint.
Sort by
Weight
Alphabetically
Computer Science
Experimental Result
100%
Threshold Voltage
100%
Time Complexity
100%
Performance Degradation
100%
Analog Circuit
100%
Simulated Annealing
100%
Physical Location
100%
Proximity Effect
100%
Design Iteration
100%
Keyphrases
Layout Dependent Effects
100%
Analog Placement
100%
Modern Analogue
100%
Oxides
25%
Process Technology
12%
Circuit Design
12%
Analog Circuits
12%
Analog Signal
12%
Traditional Design
12%
Transistor
12%
Carrier Mobility
12%
Threshold Voltage
12%
Mixed-signal Circuits
12%
Wirelength
12%
Circuit Performance
12%
Flow Effect
12%
Performance Degradation
12%
Simulated Annealing Algorithm
12%
Design Flow
12%
Post-layout Simulation
12%
Design Iteration
12%
Time Complexity
12%
Physical Location
12%
Spacing Effect
12%
B+ Tree
12%
Length Effect
12%
Fast Simulated Annealing
12%
Physics-based Model
12%
Topological Representation
12%
Packing Time
12%
Area-length
12%
Well Proximity Effect
12%
Engineering
Dependent Effect
100%
Experimental Result
12%
Circuit Design
12%
Signal Circuit
12%
Analog Circuit
12%
Circuit Performance
12%
Proximity Effect
12%
Design Flow
12%
Design Iteration
12%
Redesign
12%
Performance Degradation
12%
Simulated Annealing Algorithm
12%
Carrier Mobility
12%