On-panel electrostatic discharge (ESD) protection design with thin-film transistor in LTPS process

Ming-Dou Ker; Jie Yao Chuang; Chih Kang Deng; Chung Hong Kuo; Chun Huai Li; Ming Sheng Lai; Chih Wei Wang; Chun Ting Liu

On-panel electrostatic discharge (ESD) protection design with thin-film transistor in LTPS process

Ming-Dou Ker^*, Jie Yao Chuang, Chih Kang Deng, Chung Hong Kuo, Chun Huai Li, Ming Sheng Lai, Chih Wei Wang, Chun Ting Liu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

The electrostatic discharge (ESD) robustness of diode-connected n-type thin-film transistors (N-TFTs) and diode-connected p-type thin-film transistors (P-TFTs) with different layout structures in a given low-temperature polycrystalline silicon (LTPS) process is investigated. By using the wafer-level transmission line pulsing (TLP) system, the high-current transient characteristics and the secondary breakdown current (It2) levels of the diode-connected TFTs under different device parameters and layout structures are directly measured on the glass substrate. Finally, one set of design rules for on-panel ESD protection design is suggested.

Original language	English
Title of host publication	AD'07 - Proceedings of Asia Display 2007
Pages	551-556
Number of pages	6
State	Published - Mar 2007
Event	Asia Display 2007, AD'07 - Shanghai, China Duration: 12 Mar 2007 → 16 Mar 2007

Publication series

Name	AD'07 - Proceedings of Asia Display 2007
Volume	1

Conference

Conference	Asia Display 2007, AD'07
Country/Territory	China
City	Shanghai
Period	12/03/07 → 16/03/07

Keywords

Electrostatic discharge (ESD)Transmission line pulsing (TLP) system
Low-temperature polycrystalline silicon (LTPS)
Thin-film transistors (TFTs)

Cite this

@inproceedings{e5bc94200710445ebdf4d2cca680125c,

title = "On-panel electrostatic discharge (ESD) protection design with thin-film transistor in LTPS process",

abstract = "The electrostatic discharge (ESD) robustness of diode-connected n-type thin-film transistors (N-TFTs) and diode-connected p-type thin-film transistors (P-TFTs) with different layout structures in a given low-temperature polycrystalline silicon (LTPS) process is investigated. By using the wafer-level transmission line pulsing (TLP) system, the high-current transient characteristics and the secondary breakdown current (It2) levels of the diode-connected TFTs under different device parameters and layout structures are directly measured on the glass substrate. Finally, one set of design rules for on-panel ESD protection design is suggested.",

keywords = "Electrostatic discharge (ESD)Transmission line pulsing (TLP) system, Low-temperature polycrystalline silicon (LTPS), Thin-film transistors (TFTs)",

author = "Ming-Dou Ker and Chuang, {Jie Yao} and Deng, {Chih Kang} and Kuo, {Chung Hong} and Li, {Chun Huai} and Lai, {Ming Sheng} and Wang, {Chih Wei} and Liu, {Chun Ting}",

year = "2007",

month = mar,

language = "English",

isbn = "9787561752289",

series = "AD'07 - Proceedings of Asia Display 2007",

pages = "551--556",

booktitle = "AD'07 - Proceedings of Asia Display 2007",

note = "Asia Display 2007, AD'07 ; Conference date: 12-03-2007 Through 16-03-2007",

}

On-panel electrostatic discharge (ESD) protection design with thin-film transistor in LTPS process. / Ker, Ming-Dou; Chuang, Jie Yao; Deng, Chih Kang et al.
AD'07 - Proceedings of Asia Display 2007. 2007. p. 551-556 (AD'07 - Proceedings of Asia Display 2007; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - On-panel electrostatic discharge (ESD) protection design with thin-film transistor in LTPS process

AU - Ker, Ming-Dou

AU - Chuang, Jie Yao

AU - Deng, Chih Kang

AU - Kuo, Chung Hong

AU - Li, Chun Huai

AU - Lai, Ming Sheng

AU - Wang, Chih Wei

AU - Liu, Chun Ting

PY - 2007/3

Y1 - 2007/3

N2 - The electrostatic discharge (ESD) robustness of diode-connected n-type thin-film transistors (N-TFTs) and diode-connected p-type thin-film transistors (P-TFTs) with different layout structures in a given low-temperature polycrystalline silicon (LTPS) process is investigated. By using the wafer-level transmission line pulsing (TLP) system, the high-current transient characteristics and the secondary breakdown current (It2) levels of the diode-connected TFTs under different device parameters and layout structures are directly measured on the glass substrate. Finally, one set of design rules for on-panel ESD protection design is suggested.

AB - The electrostatic discharge (ESD) robustness of diode-connected n-type thin-film transistors (N-TFTs) and diode-connected p-type thin-film transistors (P-TFTs) with different layout structures in a given low-temperature polycrystalline silicon (LTPS) process is investigated. By using the wafer-level transmission line pulsing (TLP) system, the high-current transient characteristics and the secondary breakdown current (It2) levels of the diode-connected TFTs under different device parameters and layout structures are directly measured on the glass substrate. Finally, one set of design rules for on-panel ESD protection design is suggested.

KW - Electrostatic discharge (ESD)Transmission line pulsing (TLP) system

KW - Low-temperature polycrystalline silicon (LTPS)

KW - Thin-film transistors (TFTs)

UR - http://www.scopus.com/inward/record.url?scp=77958034301&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:77958034301

SN - 9787561752289

T3 - AD'07 - Proceedings of Asia Display 2007

SP - 551

EP - 556

BT - AD'07 - Proceedings of Asia Display 2007

T2 - Asia Display 2007, AD'07

Y2 - 12 March 2007 through 16 March 2007

ER -

On-panel electrostatic discharge (ESD) protection design with thin-film transistor in LTPS process

Abstract

Publication series

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Keywords

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