TY - GEN
T1 - On Harmonizing Data Lifetime and Block Retention Time for Flash Devices
AU - Lin, Yi Ling
AU - Yang, Ming Chang
AU - Chang, Yuan Hao
AU - Chang, Che Wei
AU - Chen, Shuo Han
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/11/15
Y1 - 2018/11/15
N2 - As the high-density flash memory, such as triple-level-cell (TLC) and 3D flash memory, has gradually dominated the market share, flash-memory-based storage devices also have suffered from the exacerbated performance and endurance problems. In order to improve the endurance of flash devices, wear-leveling and refreshing designs were proposed to evenly distribute erase operations among all flash blocks and to timely correct and re-write data of flash blocks, respectively. However, as these designs mainly aim at enhancing the endurance for flash devices, the performance issue is getting aggravated instead. Such contradiction between performance and endurance improvements drives this research to propose a time harmonization strategy, which harmonizes the block retention time with the data lifetime to enhance performance of flash devices with limited sacrifice to endurance. The experiments were conducted on trace-driven simulation with intensive and realistic workloads. Compared with the existing designs, the proposed design can effectively reduce the redundant writes by 26.8% with merely degrading the overall endurance by 0.4% on average.
AB - As the high-density flash memory, such as triple-level-cell (TLC) and 3D flash memory, has gradually dominated the market share, flash-memory-based storage devices also have suffered from the exacerbated performance and endurance problems. In order to improve the endurance of flash devices, wear-leveling and refreshing designs were proposed to evenly distribute erase operations among all flash blocks and to timely correct and re-write data of flash blocks, respectively. However, as these designs mainly aim at enhancing the endurance for flash devices, the performance issue is getting aggravated instead. Such contradiction between performance and endurance improvements drives this research to propose a time harmonization strategy, which harmonizes the block retention time with the data lifetime to enhance performance of flash devices with limited sacrifice to endurance. The experiments were conducted on trace-driven simulation with intensive and realistic workloads. Compared with the existing designs, the proposed design can effectively reduce the redundant writes by 26.8% with merely degrading the overall endurance by 0.4% on average.
KW - block retention time
KW - data lifetime
KW - data refreshing
KW - flash memory
UR - http://www.scopus.com/inward/record.url?scp=85059813439&partnerID=8YFLogxK
U2 - 10.1109/NVMSA.2018.00020
DO - 10.1109/NVMSA.2018.00020
M3 - Conference contribution
AN - SCOPUS:85059813439
T3 - Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018
SP - 73
EP - 78
BT - Proceedings - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th IEEE Non-Volatile Memory Systems and Applications Symposium, NVMSA 2018
Y2 - 28 August 2018 through 31 August 2018
ER -