TY - GEN
T1 - On-demand memory sub-system for multi-core SoCs
AU - Huang, Po-Tsang
AU - Chang, Yung
AU - Hwang, Wei
PY - 2011/12/28
Y1 - 2011/12/28
N2 - For heterogeneous multi-core SoCs, the increasing demand of the memory capacity and bandwidth becomes a critical design challenge. In this paper, an on-demand memory sub-system is presented to efficiently control the memory access and memory resource allocation using adaptively allocated cache memory. The proposed adaptively allocated cache memory can dynamically assign a variable number of SRAM banks for process elements (PEs) to optimize the utilization of the centralized on-chip cache. In a wireless video entertainment system, a 7.13% execution time reduction and 10.53% energy reduction of memories can be achieved using the adaptively allocated cache memory.
AB - For heterogeneous multi-core SoCs, the increasing demand of the memory capacity and bandwidth becomes a critical design challenge. In this paper, an on-demand memory sub-system is presented to efficiently control the memory access and memory resource allocation using adaptively allocated cache memory. The proposed adaptively allocated cache memory can dynamically assign a variable number of SRAM banks for process elements (PEs) to optimize the utilization of the centralized on-chip cache. In a wireless video entertainment system, a 7.13% execution time reduction and 10.53% energy reduction of memories can be achieved using the adaptively allocated cache memory.
UR - http://www.scopus.com/inward/record.url?scp=84255175661&partnerID=8YFLogxK
U2 - 10.1109/SOCC.2011.6085132
DO - 10.1109/SOCC.2011.6085132
M3 - Conference contribution
AN - SCOPUS:84255175661
SN - 9781457716164
T3 - International System on Chip Conference
SP - 122
EP - 127
BT - Proceedings - IEEE International SOC Conference, SOCC 2011
T2 - 24th IEEE International System on Chip Conference, SOCC 2011
Y2 - 26 September 2011 through 28 September 2011
ER -