On-chip transient detection circuit for system-level ESD protection in CMOS ICs

Ming-Dou Ker; Cheng Cheng Yen; Pi Chia Shih

doi:10.1109/CICC.2006.320949

On-chip transient detection circuit for system-level ESD protection in CMOS ICs

Ming-Dou Ker^*, Cheng Cheng Yen, Pi Chia Shih

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed in this paper. The circuit performance to detect different positive and negative fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping. The proposed transient detection circuit can be further cooperated with power-on reset circuit to improve the immunity of CMOS IC products against system-level ESD stress.

Original language	English
Title of host publication	Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Pages	361-364
Number of pages	4
DOIs	https://doi.org/10.1109/CICC.2006.320949
State	Published - 2006
Event	IEEE 2006 Custom Integrated Circuits Conference, CICC 2006 - San Jose, CA, United States Duration: 10 Sep 2006 → 13 Sep 2006

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Conference

Conference	IEEE 2006 Custom Integrated Circuits Conference, CICC 2006
Country/Territory	United States
City	San Jose, CA
Period	10/09/06 → 13/09/06

Access to Document

10.1109/CICC.2006.320949

Cite this

@inproceedings{f2ac80d6feec4ee5aac32d7c7ccec33d,

title = "On-chip transient detection circuit for system-level ESD protection in CMOS ICs",

abstract = "A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed in this paper. The circuit performance to detect different positive and negative fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping. The proposed transient detection circuit can be further cooperated with power-on reset circuit to improve the immunity of CMOS IC products against system-level ESD stress.",

author = "Ming-Dou Ker and Yen, {Cheng Cheng} and Shih, {Pi Chia}",

year = "2006",

doi = "10.1109/CICC.2006.320949",

language = "English",

isbn = "1424400767",

series = "Proceedings of the Custom Integrated Circuits Conference",

pages = "361--364",

booktitle = "Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006",

note = "IEEE 2006 Custom Integrated Circuits Conference, CICC 2006 ; Conference date: 10-09-2006 Through 13-09-2006",

}

Ker, M-D, Yen, CC & Shih, PC 2006, On-chip transient detection circuit for system-level ESD protection in CMOS ICs. in Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006., 4114979, Proceedings of the Custom Integrated Circuits Conference, pp. 361-364, IEEE 2006 Custom Integrated Circuits Conference, CICC 2006, San Jose, CA, United States, 10/09/06. https://doi.org/10.1109/CICC.2006.320949

On-chip transient detection circuit for system-level ESD protection in CMOS ICs. / Ker, Ming-Dou; Yen, Cheng Cheng; Shih, Pi Chia.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006. 2006. p. 361-364 4114979 (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Ker, Ming-Dou

AU - Yen, Cheng Cheng

AU - Shih, Pi Chia

PY - 2006

Y1 - 2006

N2 - A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed in this paper. The circuit performance to detect different positive and negative fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping. The proposed transient detection circuit can be further cooperated with power-on reset circuit to improve the immunity of CMOS IC products against system-level ESD stress.

AB - A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed in this paper. The circuit performance to detect different positive and negative fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping. The proposed transient detection circuit can be further cooperated with power-on reset circuit to improve the immunity of CMOS IC products against system-level ESD stress.

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U2 - 10.1109/CICC.2006.320949

DO - 10.1109/CICC.2006.320949

M3 - Conference contribution

AN - SCOPUS:39049141161

SN - 1424400767

SN - 9781424400768

T3 - Proceedings of the Custom Integrated Circuits Conference

SP - 361

EP - 364

BT - Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, CICC 2006

T2 - IEEE 2006 Custom Integrated Circuits Conference, CICC 2006

Y2 - 10 September 2006 through 13 September 2006

ER -

On-chip transient detection circuit for system-level ESD protection in CMOS ICs

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