On-Chip Surge Protection Structure with High Surge Robustness for USB PD 3.1 Applications

Wen Yung Ho*, Ming Dou Ker

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

An on-chip surge protection device for VBUS pins in the USB type-C interfaces is optimized to comply with USB Power Delivery (PD) 3.1 specification. Compared to the traditional PNP BJT, the new proposed PNP BJT with inserted base layout can reach higher surge and ESD robustness with relatively small area. The proposed devices fabricated in a 0.18-μm BCD technology have been measured by surge, HBM, and TLP tests to verify their immunity.

Original languageEnglish
Title of host publication2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350301649
DOIs
StatePublished - 2023
Event2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023 - Pulau Pinang, Malaysia
Duration: 24 Jul 202327 Jul 2023

Publication series

NameProceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Volume2023-July

Conference

Conference2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2023
Country/TerritoryMalaysia
CityPulau Pinang
Period24/07/2327/07/23

Keywords

  • PNP BJT
  • Surge protection device
  • USB type-C

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