On-chip ESD protection using capacitor-couple technique in 0.5-μm 3-V CMOS technology

Ming-Dou Ker; Chung-Yu Wu; Tao Cheng; Michael J.N. Wu; Ta Lee Yu

doi:10.1109/ASIC.1995.580699

On-chip ESD protection using capacitor-couple technique in 0.5-μm 3-V CMOS technology

Ming-Dou Ker^*, Chung-Yu Wu, Tao Cheng, Michael J.N. Wu, Ta Lee Yu

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

4 Scopus citations

Abstract

Capacitance-coupling effect used to lower snapback voltage and to ensure uniform ESD current distribution in the NMOS/PMOS devices of submicron CMOS on-chip ESD protection circuits is proposed. The couple capacitor is made by a ploy layer right under the wire-bonding metal pad without increasing extra layout area to the pad. By using this technique, ESD robustness of submicron CMOS IC's can be significantly improved.

Original language	English
Pages (from-to)	135-138
Number of pages	4
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs	https://doi.org/10.1109/ASIC.1995.580699
State	Published - 1 Dec 1995
Event	Proceedings of the 8th Annual IEEE International ASIC Conference and Exhibit - Austin, TX, USA Duration: 18 Sep 1995 → 22 Sep 1995

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abstract = "Capacitance-coupling effect used to lower snapback voltage and to ensure uniform ESD current distribution in the NMOS/PMOS devices of submicron CMOS on-chip ESD protection circuits is proposed. The couple capacitor is made by a ploy layer right under the wire-bonding metal pad without increasing extra layout area to the pad. By using this technique, ESD robustness of submicron CMOS IC's can be significantly improved.",

author = "Ming-Dou Ker and Chung-Yu Wu and Tao Cheng and Wu, {Michael J.N.} and Yu, {Ta Lee}",

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T1 - On-chip ESD protection using capacitor-couple technique in 0.5-μm 3-V CMOS technology

AU - Ker, Ming-Dou

AU - Wu, Chung-Yu

AU - Cheng, Tao

AU - Wu, Michael J.N.

AU - Yu, Ta Lee

PY - 1995/12/1

Y1 - 1995/12/1

N2 - Capacitance-coupling effect used to lower snapback voltage and to ensure uniform ESD current distribution in the NMOS/PMOS devices of submicron CMOS on-chip ESD protection circuits is proposed. The couple capacitor is made by a ploy layer right under the wire-bonding metal pad without increasing extra layout area to the pad. By using this technique, ESD robustness of submicron CMOS IC's can be significantly improved.

AB - Capacitance-coupling effect used to lower snapback voltage and to ensure uniform ESD current distribution in the NMOS/PMOS devices of submicron CMOS on-chip ESD protection circuits is proposed. The couple capacitor is made by a ploy layer right under the wire-bonding metal pad without increasing extra layout area to the pad. By using this technique, ESD robustness of submicron CMOS IC's can be significantly improved.

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U2 - 10.1109/ASIC.1995.580699

DO - 10.1109/ASIC.1995.580699

M3 - Conference article

AN - SCOPUS:0029542101

SN - 1063-0988

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JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Y2 - 18 September 1995 through 22 September 1995

ER -

On-chip ESD protection using capacitor-couple technique in 0.5-μm 3-V CMOS technology

Abstract

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