On-chip ESD protection design for HV integrated circuits

Ming-Dou Ker

doi:10.1109/INEC.2016.7589428

On-chip ESD protection design for HV integrated circuits

Ming-Dou Ker^*

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

Electrostatic discharge (ESD) protection has been an important reliability issue to CMOS integrated circuits, especially in high-voltage (HV) applications. In this invited talk, a brief overview on ESD protection designs for HV integrated circuits is presented. The useful and safe solutions are highlighted for real applications in HV IC products.

Original language	English
Title of host publication	7th IEEE International Nanoelectronics Conference 2016, INEC 2016
Publisher	IEEE Computer Society
ISBN (Electronic)	9781467389693
DOIs	https://doi.org/10.1109/INEC.2016.7589428
State	Published - 12 Oct 2016
Event	7th IEEE International Nanoelectronics Conference, INEC 2016 - Chengdu, China Duration: 9 May 2016 → 11 May 2016

Publication series

Name	Proceedings - International NanoElectronics Conference, INEC
Volume	2016-October
ISSN (Print)	2159-3523

Conference

Conference	7th IEEE International Nanoelectronics Conference, INEC 2016
Country/Territory	China
City	Chengdu
Period	9/05/16 → 11/05/16

Keywords

ESD protection
high-voltage (HV) IC

Access to Document

10.1109/INEC.2016.7589428

Cite this

@inproceedings{2d3af535782146ceaf812f11b84a9103,

title = "On-chip ESD protection design for HV integrated circuits",

abstract = "Electrostatic discharge (ESD) protection has been an important reliability issue to CMOS integrated circuits, especially in high-voltage (HV) applications. In this invited talk, a brief overview on ESD protection designs for HV integrated circuits is presented. The useful and safe solutions are highlighted for real applications in HV IC products.",

keywords = "ESD protection, high-voltage (HV) IC",

author = "Ming-Dou Ker",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 7th IEEE International Nanoelectronics Conference, INEC 2016 ; Conference date: 09-05-2016 Through 11-05-2016",

year = "2016",

month = oct,

day = "12",

doi = "10.1109/INEC.2016.7589428",

language = "English",

series = "Proceedings - International NanoElectronics Conference, INEC",

publisher = "IEEE Computer Society",

booktitle = "7th IEEE International Nanoelectronics Conference 2016, INEC 2016",

address = "美國",

}

Ker, M-D 2016, On-chip ESD protection design for HV integrated circuits. in 7th IEEE International Nanoelectronics Conference 2016, INEC 2016., 7589428, Proceedings - International NanoElectronics Conference, INEC, vol. 2016-October, IEEE Computer Society, 7th IEEE International Nanoelectronics Conference, INEC 2016, Chengdu, China, 9/05/16. https://doi.org/10.1109/INEC.2016.7589428

TY - GEN

T1 - On-chip ESD protection design for HV integrated circuits

AU - Ker, Ming-Dou

PY - 2016/10/12

Y1 - 2016/10/12

N2 - Electrostatic discharge (ESD) protection has been an important reliability issue to CMOS integrated circuits, especially in high-voltage (HV) applications. In this invited talk, a brief overview on ESD protection designs for HV integrated circuits is presented. The useful and safe solutions are highlighted for real applications in HV IC products.

AB - Electrostatic discharge (ESD) protection has been an important reliability issue to CMOS integrated circuits, especially in high-voltage (HV) applications. In this invited talk, a brief overview on ESD protection designs for HV integrated circuits is presented. The useful and safe solutions are highlighted for real applications in HV IC products.

KW - ESD protection

KW - high-voltage (HV) IC

UR - http://www.scopus.com/inward/record.url?scp=84992694529&partnerID=8YFLogxK

U2 - 10.1109/INEC.2016.7589428

DO - 10.1109/INEC.2016.7589428

M3 - Conference contribution

AN - SCOPUS:84992694529

T3 - Proceedings - International NanoElectronics Conference, INEC

BT - 7th IEEE International Nanoelectronics Conference 2016, INEC 2016

PB - IEEE Computer Society

T2 - 7th IEEE International Nanoelectronics Conference, INEC 2016

Y2 - 9 May 2016 through 11 May 2016

ER -

On-chip ESD protection design for HV integrated circuits

Abstract

Publication series

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this