On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application

Tai Ho Wang; Ming-Dou Ker

doi:10.1109/EOSESD.2000.890086

On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application

Tai Ho Wang^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

7 Scopus citations

Abstract

A novel on-chip ESD protection design by using polysilicon diodes for smart card application is reported in this paper. By adding an efficient VDD-to-VSS clamp circuit, the HBM ESD level of the smart card IC with polysilicon diodes as the ESD protection devices have been successfully improved from the original approximately 300 V to become ≥3 kV. Different process splits have been experimentally evaluated to find the suitable doping concentration for optimizing, the polysilicon diodes for both smart card application and on-chip ESD protection design.

Original language	English
Article number	890086
Pages (from-to)	266-275
Number of pages	10
Journal	Electrical Overstress/Electrostatic Discharge Symposium Proceedings
DOIs	https://doi.org/10.1109/EOSESD.2000.890086
State	Published - 26 Sep 2000
Event	Electrical Overstress/Electrostatic Discharge Symposium Proceedings - Anaheim, CA, USA Duration: 26 Sep 2000 → 28 Sep 2000

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title = "On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application",

abstract = "A novel on-chip ESD protection design by using polysilicon diodes for smart card application is reported in this paper. By adding an efficient VDD-to-VSS clamp circuit, the HBM ESD level of the smart card IC with polysilicon diodes as the ESD protection devices have been successfully improved from the original approximately 300 V to become ≥3 kV. Different process splits have been experimentally evaluated to find the suitable doping concentration for optimizing, the polysilicon diodes for both smart card application and on-chip ESD protection design.",

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year = "2000",

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AU - Ker, Ming-Dou

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N2 - A novel on-chip ESD protection design by using polysilicon diodes for smart card application is reported in this paper. By adding an efficient VDD-to-VSS clamp circuit, the HBM ESD level of the smart card IC with polysilicon diodes as the ESD protection devices have been successfully improved from the original approximately 300 V to become ≥3 kV. Different process splits have been experimentally evaluated to find the suitable doping concentration for optimizing, the polysilicon diodes for both smart card application and on-chip ESD protection design.

AB - A novel on-chip ESD protection design by using polysilicon diodes for smart card application is reported in this paper. By adding an efficient VDD-to-VSS clamp circuit, the HBM ESD level of the smart card IC with polysilicon diodes as the ESD protection devices have been successfully improved from the original approximately 300 V to become ≥3 kV. Different process splits have been experimentally evaluated to find the suitable doping concentration for optimizing, the polysilicon diodes for both smart card application and on-chip ESD protection design.

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U2 - 10.1109/EOSESD.2000.890086

DO - 10.1109/EOSESD.2000.890086

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AN - SCOPUS:0034544873

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JO - Electrical Overstress/Electrostatic Discharge Symposium Proceedings

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M1 - 890086

Y2 - 26 September 2000 through 28 September 2000

ER -

On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application

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