On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process

Ming-Dou Ker; Kuo Chun Hsu

doi:10.1109/ISCAS.2002.1010757

On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process

Ming-Dou Ker^*, Kuo Chun Hsu

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

5 Scopus citations

Abstract

A novel design concept to turn on the SCR device by applying the substrate-triggered method is first proposed in the literature for effective on-chip ESD protection design. To avoid the transient-induced latch-up issue, the substrate-triggered SCR devices are stacked in the ESD protection circuits. The turn-on efficiency of SCR can be greatly improved by applying the substrate-triggered method. The on-chip ESD protection circuits designed with the substrate-triggered SCR devices for input pad, output pad, and power pad have been successfully verified in a 0.25-μm CMOS process. The substrate-triggered SCR device with a smaller layout area of only 40μm×20μm can sustain the HBM ESD stress of higher than 7kV.

Original language	English
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	5
DOIs	https://doi.org/10.1109/ISCAS.2002.1010757
State	Published - 1 Jan 2002
Event	2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States Duration: 26 May 2002 → 29 May 2002

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title = "On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process",

abstract = "A novel design concept to turn on the SCR device by applying the substrate-triggered method is first proposed in the literature for effective on-chip ESD protection design. To avoid the transient-induced latch-up issue, the substrate-triggered SCR devices are stacked in the ESD protection circuits. The turn-on efficiency of SCR can be greatly improved by applying the substrate-triggered method. The on-chip ESD protection circuits designed with the substrate-triggered SCR devices for input pad, output pad, and power pad have been successfully verified in a 0.25-μm CMOS process. The substrate-triggered SCR device with a smaller layout area of only 40μm×20μm can sustain the HBM ESD stress of higher than 7kV.",

author = "Ming-Dou Ker and Hsu, {Kuo Chun}",

year = "2002",

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doi = "10.1109/ISCAS.2002.1010757",

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T1 - On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process

AU - Ker, Ming-Dou

AU - Hsu, Kuo Chun

PY - 2002/1/1

Y1 - 2002/1/1

N2 - A novel design concept to turn on the SCR device by applying the substrate-triggered method is first proposed in the literature for effective on-chip ESD protection design. To avoid the transient-induced latch-up issue, the substrate-triggered SCR devices are stacked in the ESD protection circuits. The turn-on efficiency of SCR can be greatly improved by applying the substrate-triggered method. The on-chip ESD protection circuits designed with the substrate-triggered SCR devices for input pad, output pad, and power pad have been successfully verified in a 0.25-μm CMOS process. The substrate-triggered SCR device with a smaller layout area of only 40μm×20μm can sustain the HBM ESD stress of higher than 7kV.

AB - A novel design concept to turn on the SCR device by applying the substrate-triggered method is first proposed in the literature for effective on-chip ESD protection design. To avoid the transient-induced latch-up issue, the substrate-triggered SCR devices are stacked in the ESD protection circuits. The turn-on efficiency of SCR can be greatly improved by applying the substrate-triggered method. The on-chip ESD protection circuits designed with the substrate-triggered SCR devices for input pad, output pad, and power pad have been successfully verified in a 0.25-μm CMOS process. The substrate-triggered SCR device with a smaller layout area of only 40μm×20μm can sustain the HBM ESD stress of higher than 7kV.

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DO - 10.1109/ISCAS.2002.1010757

M3 - Conference article

AN - SCOPUS:0036287788

SN - 0271-4310

VL - 5

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

Y2 - 26 May 2002 through 29 May 2002

ER -

On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process

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