On-chip ESD detection circuit for system-level ESD protection design

Ming-Dou Ker*, Wan Yen Lin, Cheng Cheng Yen, Che Ming Yang, Tung Yang Chen, Shih Fan Chen

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    9 Scopus citations

    Abstract

    A new on-chip CR-based electrostatic discharge (ESD) detection circuit for system-level ESD protection design is proposed in this work. The circuit performance to detect positive or negative electrical transients generated by system-level ESD tests has been analyzed in HSPICE simulation and verified in silicon chip. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed detection circuit can detect ESD-induced transient disturbance during system-level ESD zapping. The detection results can be used as system recovery firmware index to improve the immunity of CMOS IC products against system-level ESD stress.

    Original languageEnglish
    Title of host publicationICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
    Pages1584-1587
    Number of pages4
    DOIs
    StatePublished - 1 Dec 2010
    Event2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
    Duration: 1 Nov 20104 Nov 2010

    Publication series

    NameICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

    Conference

    Conference2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
    Country/TerritoryChina
    CityShanghai
    Period1/11/104/11/10

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