On-chip ESD detection circuit for system-level ESD protection design

Ming-Dou Ker; Wan Yen Lin; Cheng Cheng Yen; Che Ming Yang; Tung Yang Chen; Shih Fan Chen

doi:10.1109/ICSICT.2010.5667447

On-chip ESD detection circuit for system-level ESD protection design

Ming-Dou Ker^*, Wan Yen Lin, Cheng Cheng Yen, Che Ming Yang, Tung Yang Chen, Shih Fan Chen

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Scopus citations

Abstract

A new on-chip CR-based electrostatic discharge (ESD) detection circuit for system-level ESD protection design is proposed in this work. The circuit performance to detect positive or negative electrical transients generated by system-level ESD tests has been analyzed in HSPICE simulation and verified in silicon chip. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed detection circuit can detect ESD-induced transient disturbance during system-level ESD zapping. The detection results can be used as system recovery firmware index to improve the immunity of CMOS IC products against system-level ESD stress.

Original language	English
Title of host publication	ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Pages	1584-1587
Number of pages	4
DOIs	https://doi.org/10.1109/ICSICT.2010.5667447
State	Published - 1 Dec 2010
Event	2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China Duration: 1 Nov 2010 → 4 Nov 2010

Publication series

Name	ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Conference

Conference	2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
Country/Territory	China
City	Shanghai
Period	1/11/10 → 4/11/10

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10.1109/ICSICT.2010.5667447

Cite this

Ker, M-D., Lin, W. Y., Yen, C. C., Yang, C. M., Chen, T. Y., & Chen, S. F. (2010). On-chip ESD detection circuit for system-level ESD protection design. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 1584-1587). [5667447] (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2010.5667447

Ker, Ming-Dou ; Lin, Wan Yen ; Yen, Cheng Cheng et al. / On-chip ESD detection circuit for system-level ESD protection design. ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. pp. 1584-1587 (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

@inproceedings{8410911aaedb49c99aa25089606d0abd,

title = "On-chip ESD detection circuit for system-level ESD protection design",

abstract = "A new on-chip CR-based electrostatic discharge (ESD) detection circuit for system-level ESD protection design is proposed in this work. The circuit performance to detect positive or negative electrical transients generated by system-level ESD tests has been analyzed in HSPICE simulation and verified in silicon chip. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed detection circuit can detect ESD-induced transient disturbance during system-level ESD zapping. The detection results can be used as system recovery firmware index to improve the immunity of CMOS IC products against system-level ESD stress.",

author = "Ming-Dou Ker and Lin, {Wan Yen} and Yen, {Cheng Cheng} and Yang, {Che Ming} and Chen, {Tung Yang} and Chen, {Shih Fan}",

year = "2010",

month = dec,

day = "1",

doi = "10.1109/ICSICT.2010.5667447",

language = "English",

isbn = "9781424457984",

series = "ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

pages = "1584--1587",

booktitle = "ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

note = "2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology ; Conference date: 01-11-2010 Through 04-11-2010",

}

Ker, M-D, Lin, WY, Yen, CC, Yang, CM, Chen, TY & Chen, SF 2010, On-chip ESD detection circuit for system-level ESD protection design. in ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 5667447, ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings, pp. 1584-1587, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 1/11/10. https://doi.org/10.1109/ICSICT.2010.5667447

On-chip ESD detection circuit for system-level ESD protection design. / Ker, Ming-Dou; Lin, Wan Yen; Yen, Cheng Cheng et al.
ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. p. 1584-1587 5667447 (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - On-chip ESD detection circuit for system-level ESD protection design

AU - Ker, Ming-Dou

AU - Lin, Wan Yen

AU - Yen, Cheng Cheng

AU - Yang, Che Ming

AU - Chen, Tung Yang

AU - Chen, Shih Fan

PY - 2010/12/1

Y1 - 2010/12/1

N2 - A new on-chip CR-based electrostatic discharge (ESD) detection circuit for system-level ESD protection design is proposed in this work. The circuit performance to detect positive or negative electrical transients generated by system-level ESD tests has been analyzed in HSPICE simulation and verified in silicon chip. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed detection circuit can detect ESD-induced transient disturbance during system-level ESD zapping. The detection results can be used as system recovery firmware index to improve the immunity of CMOS IC products against system-level ESD stress.

AB - A new on-chip CR-based electrostatic discharge (ESD) detection circuit for system-level ESD protection design is proposed in this work. The circuit performance to detect positive or negative electrical transients generated by system-level ESD tests has been analyzed in HSPICE simulation and verified in silicon chip. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed detection circuit can detect ESD-induced transient disturbance during system-level ESD zapping. The detection results can be used as system recovery firmware index to improve the immunity of CMOS IC products against system-level ESD stress.

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U2 - 10.1109/ICSICT.2010.5667447

DO - 10.1109/ICSICT.2010.5667447

M3 - Conference contribution

AN - SCOPUS:78751492044

SN - 9781424457984

T3 - ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

SP - 1584

EP - 1587

BT - ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

T2 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

Y2 - 1 November 2010 through 4 November 2010

ER -

Ker M-D, Lin WY, Yen CC, Yang CM, Chen TY, Chen SF. On-chip ESD detection circuit for system-level ESD protection design. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. p. 1584-1587. 5667447. (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings). doi: 10.1109/ICSICT.2010.5667447

On-chip ESD detection circuit for system-level ESD protection design

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