On board processor development for NASA's spacebone imaging radar with VLSI system-on-chip technology

Wai-Chi  Fang*, Michael Y. Jin

*Corresponding author for this work

Research output: Contribution to journalConference articlepeer-review

15 Scopus citations

Abstract

This paper reports a preliminary study result of an on-board spaceborne SAR processor. It consists of a processing requirement analysis, functional specifications, and implementation with VLSI system-on-chip technology. Finally, a minimum version of this VLSI on-board processor designed for performance evaluation and for partial demonstration is illustrated.

Original languageEnglish
Pages (from-to)II901-II904
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume2
DOIs
StatePublished - 2004
Event2004 IEEE International Symposium on Cirquits and Systems - Proceedings - Vancouver, BC, Canada
Duration: 23 May 200426 May 2004

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