On-board fault-tolerant SAR processor for spaceborne imaging radar systems

Wai-Chi  Fang; Charles Le; Stephanie Taft

doi:10.1109/ISCAS.2005.1464614

On-board fault-tolerant SAR processor for spaceborne imaging radar systems

Wai-Chi Fang^*, Charles Le, Stephanie Taft

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

11 Scopus citations

Abstract

A real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images has been developed for advanced spaceborne radar imaging systems. In this paper, we present the integrated design approach, from top-level algorithm specifications, system architectures, design methodology, functional verification, performance validation, down to hardware design and implementation.

Original language	English
Article number	1464614
Pages (from-to)	420-423
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1464614
State	Published - 1 Dec 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 23 May 2005 → 26 May 2005

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title = "On-board fault-tolerant SAR processor for spaceborne imaging radar systems",

abstract = "A real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images has been developed for advanced spaceborne radar imaging systems. In this paper, we present the integrated design approach, from top-level algorithm specifications, system architectures, design methodology, functional verification, performance validation, down to hardware design and implementation.",

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AU - Le, Charles

AU - Taft, Stephanie

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AB - A real-time high-performance and fault-tolerant FPGA-based hardware architecture for the processing of synthetic aperture radar (SAR) images has been developed for advanced spaceborne radar imaging systems. In this paper, we present the integrated design approach, from top-level algorithm specifications, system architectures, design methodology, functional verification, performance validation, down to hardware design and implementation.

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ER -

On-board fault-tolerant SAR processor for spaceborne imaging radar systems

Abstract

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