Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs

Yi-Ming Li

doi:10.1007/s10825-006-0020-y

Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs

Yi-Ming Li^*

^*Corresponding author for this work

Department of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

In this paper, electrical characteristics of 25 nm strained fin-typed field effect transistors (FinFETs) with oxide-nitride-stacked-capping layer are numerically studied. The FinFETs are fabricated on two different wafers, one is bulk silicon and the other is silicon-on-insulator (SOI) substrate. A three-dimensional device simulation is performed by solving a set of density-gradient-hydrodynamic equations to study device performance including, such as the drain current characteristics (the I_D -V_G and I_D-V_D curves), the drain-induced barrier height lowering, and the subthreshold swing. Comparison between the strained bulk and SOI FinFETs shows that the strained bulk FinFET is promising for emerging multiple-gate nanodevice era according to the manufacturability point of view.

Original language	English
Pages (from-to)	371-376
Number of pages	6
Journal	Journal of Computational Electronics
Volume	5
Issue number	4
DOIs	https://doi.org/10.1007/s10825-006-0020-y
State	Published - Dec 2006

Keywords

Device simulation
Drain current
Drain-induced barrier height lowering
Electrical characteristics
Strained SOI FinFET
Strained bulk FinFET
Subthreshold swing

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10.1007/s10825-006-0020-y

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title = "Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs",

abstract = "In this paper, electrical characteristics of 25 nm strained fin-typed field effect transistors (FinFETs) with oxide-nitride-stacked-capping layer are numerically studied. The FinFETs are fabricated on two different wafers, one is bulk silicon and the other is silicon-on-insulator (SOI) substrate. A three-dimensional device simulation is performed by solving a set of density-gradient-hydrodynamic equations to study device performance including, such as the drain current characteristics (the ID -VG and ID-VD curves), the drain-induced barrier height lowering, and the subthreshold swing. Comparison between the strained bulk and SOI FinFETs shows that the strained bulk FinFET is promising for emerging multiple-gate nanodevice era according to the manufacturability point of view.",

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author = "Yi-Ming Li",

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T1 - Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs

AU - Li, Yi-Ming

PY - 2006/12

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N2 - In this paper, electrical characteristics of 25 nm strained fin-typed field effect transistors (FinFETs) with oxide-nitride-stacked-capping layer are numerically studied. The FinFETs are fabricated on two different wafers, one is bulk silicon and the other is silicon-on-insulator (SOI) substrate. A three-dimensional device simulation is performed by solving a set of density-gradient-hydrodynamic equations to study device performance including, such as the drain current characteristics (the ID -VG and ID-VD curves), the drain-induced barrier height lowering, and the subthreshold swing. Comparison between the strained bulk and SOI FinFETs shows that the strained bulk FinFET is promising for emerging multiple-gate nanodevice era according to the manufacturability point of view.

AB - In this paper, electrical characteristics of 25 nm strained fin-typed field effect transistors (FinFETs) with oxide-nitride-stacked-capping layer are numerically studied. The FinFETs are fabricated on two different wafers, one is bulk silicon and the other is silicon-on-insulator (SOI) substrate. A three-dimensional device simulation is performed by solving a set of density-gradient-hydrodynamic equations to study device performance including, such as the drain current characteristics (the ID -VG and ID-VD curves), the drain-induced barrier height lowering, and the subthreshold swing. Comparison between the strained bulk and SOI FinFETs shows that the strained bulk FinFET is promising for emerging multiple-gate nanodevice era according to the manufacturability point of view.

KW - Device simulation

KW - Drain current

KW - Drain-induced barrier height lowering

KW - Electrical characteristics

KW - Strained SOI FinFET

KW - Strained bulk FinFET

KW - Subthreshold swing

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DO - 10.1007/s10825-006-0020-y

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JO - Journal of Computational Electronics

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ER -

Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs

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Keywords

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