TY - GEN
T1 - Novel FFT processor with parallel-in-parallel-out in normal order
AU - Hu, Hsiang Sheng
AU - Chen, Hsiao Yun
AU - Jou, Shyh-Jye
PY - 2009/12/1
Y1 - 2009/12/1
N2 -
A novel FFT processor that can provide parallel-in-parallel- out in normal order is proposed for high throughput required OFDM communication system, such as discrete Fourier transform (DFT)-based channel estimation in IEEE 802.16e. The hardware implementation results show the proposed 1024-point FFT architecture can achieve the throughput rate up to 1.28 G samples/sec and the execution time down to 7.3 us when working at 160 MHz. When working at the system required 83.3 MHz, it consumes 21.7 mW with 134474 gates (including memory) that occupy 0.471 mm
2
by using 90 nm, 1V CMOS process.
AB -
A novel FFT processor that can provide parallel-in-parallel- out in normal order is proposed for high throughput required OFDM communication system, such as discrete Fourier transform (DFT)-based channel estimation in IEEE 802.16e. The hardware implementation results show the proposed 1024-point FFT architecture can achieve the throughput rate up to 1.28 G samples/sec and the execution time down to 7.3 us when working at 160 MHz. When working at the system required 83.3 MHz, it consumes 21.7 mW with 134474 gates (including memory) that occupy 0.471 mm
2
by using 90 nm, 1V CMOS process.
UR - http://www.scopus.com/inward/record.url?scp=77950682911&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2009.5158117
DO - 10.1109/VDAT.2009.5158117
M3 - Conference contribution
AN - SCOPUS:77950682911
SN - 9781424427826
T3 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
SP - 150
EP - 153
BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
T2 - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Y2 - 28 April 2009 through 30 April 2009
ER -