Novel FFT processor with parallel-in-parallel-out in normal order

Hsiang Sheng Hu; Hsiao Yun Chen; Shyh-Jye Jou

doi:10.1109/VDAT.2009.5158117

Novel FFT processor with parallel-in-parallel-out in normal order

Hsiang Sheng Hu^*, Hsiao Yun Chen, Shyh-Jye Jou

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

A novel FFT processor that can provide parallel-in-parallel- out in normal order is proposed for high throughput required OFDM communication system, such as discrete Fourier transform (DFT)-based channel estimation in IEEE 802.16e. The hardware implementation results show the proposed 1024-point FFT architecture can achieve the throughput rate up to 1.28 G samples/sec and the execution time down to 7.3 us when working at 160 MHz. When working at the system required 83.3 MHz, it consumes 21.7 mW with 134474 gates (including memory) that occupy 0.471 mm ² by using 90 nm, 1V CMOS process.

Original language	English
Title of host publication	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Pages	150-153
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2009.5158117
State	Published - 1 Dec 2009
Event	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 - Hsinchu, Taiwan Duration: 28 Apr 2009 → 30 Apr 2009

Publication series

Name	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Conference

Conference	2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09
Country/Territory	Taiwan
City	Hsinchu
Period	28/04/09 → 30/04/09

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10.1109/VDAT.2009.5158117

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@inproceedings{37a0b181c459444f96c17ee0762f76b9,

title = "Novel FFT processor with parallel-in-parallel-out in normal order",

abstract = " A novel FFT processor that can provide parallel-in-parallel- out in normal order is proposed for high throughput required OFDM communication system, such as discrete Fourier transform (DFT)-based channel estimation in IEEE 802.16e. The hardware implementation results show the proposed 1024-point FFT architecture can achieve the throughput rate up to 1.28 G samples/sec and the execution time down to 7.3 us when working at 160 MHz. When working at the system required 83.3 MHz, it consumes 21.7 mW with 134474 gates (including memory) that occupy 0.471 mm 2 by using 90 nm, 1V CMOS process.",

author = "Hu, {Hsiang Sheng} and Chen, {Hsiao Yun} and Shyh-Jye Jou",

year = "2009",

month = dec,

day = "1",

doi = "10.1109/VDAT.2009.5158117",

language = "English",

isbn = "9781424427826",

series = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

pages = "150--153",

booktitle = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",

note = "null ; Conference date: 28-04-2009 Through 30-04-2009",

}

Hu, HS, Chen, HY & Jou, S-J 2009, Novel FFT processor with parallel-in-parallel-out in normal order. in 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09., 5158117, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, pp. 150-153, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09, Hsinchu, Taiwan, 28/04/09. https://doi.org/10.1109/VDAT.2009.5158117

Novel FFT processor with parallel-in-parallel-out in normal order. / Hu, Hsiang Sheng; Chen, Hsiao Yun; Jou, Shyh-Jye.

2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. 2009. p. 150-153 5158117 (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - A novel FFT processor that can provide parallel-in-parallel- out in normal order is proposed for high throughput required OFDM communication system, such as discrete Fourier transform (DFT)-based channel estimation in IEEE 802.16e. The hardware implementation results show the proposed 1024-point FFT architecture can achieve the throughput rate up to 1.28 G samples/sec and the execution time down to 7.3 us when working at 160 MHz. When working at the system required 83.3 MHz, it consumes 21.7 mW with 134474 gates (including memory) that occupy 0.471 mm 2 by using 90 nm, 1V CMOS process.

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BT - 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

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Novel FFT processor with parallel-in-parallel-out in normal order

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