@inproceedings{9bb443280d8f4c138c5f52dde54c98f2,
title = "Novel ESD implantation for sub-quarter-micron CMOS technology with enhanced machine-model ESD robustness",
abstract = "A novel ESD implantation method is proposed to significantly improve machine-model (MM) electrostatic discharge (ESD) robustness of CMOS integrated circuits in sub-quarter-micron CMOS processes. By using this method, the ESD current is discharged far away from the surface channel of NMOS, therefore the NMOS can sustain a much higher ESD level, especially under the machine-model ESD stress. The MM ESD robustness of the gate-grounded NMOS (ggNMOS) with a device dimension of W/L= 300 μm/0.5 μm has been successfully improved from the original 450 V to become 675 V in a 0.25 μm CMOS process.",
keywords = "CMOS integrated circuits, CMOS process, CMOS technology, Current measurement, Electrostatic discharge, Integrated circuit modeling, MOS devices, Robustness, Semiconductor device modeling, Stress",
author = "Ming-Dou Ker and Hsu, {Hsin Chyh} and Peng, {Jeng Jie}",
year = "2002",
month = jan,
day = "1",
doi = "10.1109/IPFA.2002.1025614",
language = "English",
series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "70--74",
editor = "Chim, {Wai Kin} and John Thong and Wilson Tan and Lee, {Kheng Chooi}",
booktitle = "Proceedings of the 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002",
address = "美國",
note = "9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2002 ; Conference date: 12-07-2002",
}