Novel diode structures and ESD protection circuits in a 1.8-V 0.15-μm partially-depleted SOI salicided CMOS process

Ming-Dou Ker*, K. K. Hung, H. T.H. Tang, S. C. Huang, S. S. Chen, M. C. Wang

*Corresponding author for this work

    Research output: Contribution to conferencePaperpeer-review

    15 Scopus citations

    Abstract

    I-V characteristics, ESD robustness, and It2 of the gated and non-gated diode structures for ESD protection in a 0.15-μ-m partially-depleted silicon-on-insulator CMOS technology were studied and compared to that of Lubistor diode. A novel gate-triggered design on the power-rail ESD clamp circuit with the gated diodes in stacked configuration showed a higher ESD robustness and faster turn-on speed to effectively protect the devices of internal circuits.

    Original languageAmerican English
    Pages91-96
    Number of pages6
    DOIs
    StatePublished - Jul 2001
    Event8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) - Singapure, Singapore
    Duration: 9 Jul 200113 Jul 2001

    Conference

    Conference8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001)
    Country/TerritorySingapore
    CitySingapure
    Period9/07/0113/07/01

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