I-V characteristics, ESD robustness, and It2 of the gated and non-gated diode structures for ESD protection in a 0.15-μ-m partially-depleted silicon-on-insulator CMOS technology were studied and compared to that of Lubistor diode. A novel gate-triggered design on the power-rail ESD clamp circuit with the gated diodes in stacked configuration showed a higher ESD robustness and faster turn-on speed to effectively protect the devices of internal circuits.
|Number of pages
|Published - Jul 2001
|8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) - Singapure, Singapore
Duration: 9 Jul 2001 → 13 Jul 2001
|8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001)
|9/07/01 → 13/07/01