Novel diode structures and ESD protection circuits in a 1.8-V 0.15-μm partially-depleted SOI salicided CMOS process

Ming-Dou Ker; K. K. Hung; H. T.H. Tang; S. C. Huang; S. S. Chen; M. C. Wang

doi:10.1109/IPFA.2001.941462

Novel diode structures and ESD protection circuits in a 1.8-V 0.15-μm partially-depleted SOI salicided CMOS process

Ming-Dou Ker^*, K. K. Hung, H. T.H. Tang, S. C. Huang, S. S. Chen, M. C. Wang

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

16 Scopus citations

Abstract

I-V characteristics, ESD robustness, and It2 of the gated and non-gated diode structures for ESD protection in a 0.15-μ-m partially-depleted silicon-on-insulator CMOS technology were studied and compared to that of Lubistor diode. A novel gate-triggered design on the power-rail ESD clamp circuit with the gated diodes in stacked configuration showed a higher ESD robustness and faster turn-on speed to effectively protect the devices of internal circuits.

Original language	American English
Pages	91-96
Number of pages	6
DOIs	https://doi.org/10.1109/IPFA.2001.941462
State	Published - Jul 2001
Event	8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) - Singapure, Singapore Duration: 9 Jul 2001 → 13 Jul 2001

Conference

Conference	8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001)
Country/Territory	Singapore
City	Singapure
Period	9/07/01 → 13/07/01

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10.1109/IPFA.2001.941462

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Ker, M.-D., Hung, K. K., Tang, H. T. H., Huang, S. C., Chen, S. S., & Wang, M. C. (2001). Novel diode structures and ESD protection circuits in a 1.8-V 0.15-μm partially-depleted SOI salicided CMOS process. 91-96. Paper presented at 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001), Singapure, Singapore. https://doi.org/10.1109/IPFA.2001.941462

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title = "Novel diode structures and ESD protection circuits in a 1.8-V 0.15-μm partially-depleted SOI salicided CMOS process",

abstract = "I-V characteristics, ESD robustness, and It2 of the gated and non-gated diode structures for ESD protection in a 0.15-μ-m partially-depleted silicon-on-insulator CMOS technology were studied and compared to that of Lubistor diode. A novel gate-triggered design on the power-rail ESD clamp circuit with the gated diodes in stacked configuration showed a higher ESD robustness and faster turn-on speed to effectively protect the devices of internal circuits.",

author = "Ming-Dou Ker and Hung, {K. K.} and Tang, {H. T.H.} and Huang, {S. C.} and Chen, {S. S.} and Wang, {M. C.}",

year = "2001",

month = jul,

doi = "10.1109/IPFA.2001.941462",

language = "American English",

pages = "91--96",

note = "8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) ; Conference date: 09-07-2001 Through 13-07-2001",

}

Ker, M-D, Hung, KK, Tang, HTH, Huang, SC, Chen, SS & Wang, MC 2001, 'Novel diode structures and ESD protection circuits in a 1.8-V 0.15-μm partially-depleted SOI salicided CMOS process', Paper presented at 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001), Singapure, Singapore, 9/07/01 - 13/07/01 pp. 91-96. https://doi.org/10.1109/IPFA.2001.941462

Novel diode structures and ESD protection circuits in a 1.8-V 0.15-μm partially-depleted SOI salicided CMOS process. / Ker, Ming-Dou; Hung, K. K.; Tang, H. T.H. et al.
2001. 91-96 Paper presented at 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001), Singapure, Singapore.

Research output: Contribution to conference › Paper › peer-review

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AU - Hung, K. K.

AU - Tang, H. T.H.

AU - Huang, S. C.

AU - Chen, S. S.

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N2 - I-V characteristics, ESD robustness, and It2 of the gated and non-gated diode structures for ESD protection in a 0.15-μ-m partially-depleted silicon-on-insulator CMOS technology were studied and compared to that of Lubistor diode. A novel gate-triggered design on the power-rail ESD clamp circuit with the gated diodes in stacked configuration showed a higher ESD robustness and faster turn-on speed to effectively protect the devices of internal circuits.

AB - I-V characteristics, ESD robustness, and It2 of the gated and non-gated diode structures for ESD protection in a 0.15-μ-m partially-depleted silicon-on-insulator CMOS technology were studied and compared to that of Lubistor diode. A novel gate-triggered design on the power-rail ESD clamp circuit with the gated diodes in stacked configuration showed a higher ESD robustness and faster turn-on speed to effectively protect the devices of internal circuits.

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ER -

Novel diode structures and ESD protection circuits in a 1.8-V 0.15-μm partially-depleted SOI salicided CMOS process

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