Novel design for testability of a mixed-signal VLSIC

E. McShane; K. Shenai; L. Alkalai; E. Kolawa; V. Boyadzhyan; B. Blaes; Wai-Chi  Fang

doi:10.1109/GLSV.1999.757385

Novel design for testability of a mixed-signal VLSIC

E. McShane^*, K. Shenai, L. Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, Wai-Chi Fang

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

A novel testability architecture has been developed for a mixed-signal VLSIC which has a functional architecture consisting of a microprocessor core, RF transceiver, and two voltage regulators. It permits a decoupling of analog/RF, digital, and power systems for individual stimulation and analysis. Testing may be performed at the subsystem or block level, and traditional scan techniques are augmented to allow mixed static and dynamic test. This approach aids in identifying any detrimental interaction between individual subsystems by providing isolated between the circuit-under-test and idle circuits.

Original language	English
Title of host publication	Proceedings of the IEEE Great Lakes Symposium on VLSI
Publisher	IEEE
Pages	97-100
Number of pages	4
ISBN (Print)	0769501044
DOIs	https://doi.org/10.1109/GLSV.1999.757385
State	Published - 1999
Event	Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA Duration: 4 Mar 1999 → 6 Mar 1999

Publication series

Name	Proceedings of the IEEE Great Lakes Symposium on VLSI
ISSN (Print)	1066-1395

Conference

Conference	Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99)
City	Ann Arbor, MI, USA
Period	4/03/99 → 6/03/99

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This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/GLSV.1999.757385

Cite this

@inproceedings{9e0306c18099410cb08a47e5e969cc4c,

title = "Novel design for testability of a mixed-signal VLSIC",

abstract = "A novel testability architecture has been developed for a mixed-signal VLSIC which has a functional architecture consisting of a microprocessor core, RF transceiver, and two voltage regulators. It permits a decoupling of analog/RF, digital, and power systems for individual stimulation and analysis. Testing may be performed at the subsystem or block level, and traditional scan techniques are augmented to allow mixed static and dynamic test. This approach aids in identifying any detrimental interaction between individual subsystems by providing isolated between the circuit-under-test and idle circuits.",

author = "E. McShane and K. Shenai and L. Alkalai and E. Kolawa and V. Boyadzhyan and B. Blaes and Wai-Chi Fang",

year = "1999",

doi = "10.1109/GLSV.1999.757385",

language = "English",

isbn = "0769501044",

series = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

publisher = "IEEE",

pages = "97--100",

booktitle = "Proceedings of the IEEE Great Lakes Symposium on VLSI",

note = "Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) ; Conference date: 04-03-1999 Through 06-03-1999",

}

McShane, E, Shenai, K, Alkalai, L, Kolawa, E, Boyadzhyan, V, Blaes, B & Fang, W-C 1999, Novel design for testability of a mixed-signal VLSIC. in Proceedings of the IEEE Great Lakes Symposium on VLSI. Proceedings of the IEEE Great Lakes Symposium on VLSI, IEEE, pp. 97-100, Proceedings of the 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99), Ann Arbor, MI, USA, 4/03/99. https://doi.org/10.1109/GLSV.1999.757385

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AU - Shenai, K.

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AU - Kolawa, E.

AU - Boyadzhyan, V.

AU - Blaes, B.

AU - Fang, Wai-Chi

PY - 1999

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AB - A novel testability architecture has been developed for a mixed-signal VLSIC which has a functional architecture consisting of a microprocessor core, RF transceiver, and two voltage regulators. It permits a decoupling of analog/RF, digital, and power systems for individual stimulation and analysis. Testing may be performed at the subsystem or block level, and traditional scan techniques are augmented to allow mixed static and dynamic test. This approach aids in identifying any detrimental interaction between individual subsystems by providing isolated between the circuit-under-test and idle circuits.

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ER -

Novel design for testability of a mixed-signal VLSIC

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