A robust CMOS on-chip ESD/EOS protection circuit is proposed, which consists of four parasitic lateral SCR devices with low ESD trigger voltages to protect NMOS and PMOS devices of the internal circuits against the ESD pulses with both positive and negative polarities with respect to either VDD or VSS(GND) nodes. For each ESD stress with positive or negative polarity, there is an efficient and direct shunt path generated by the SCR low- impedance latching state to quickly bypass the ESD current. Thus this novel full-SCR ESD protection circuit can perform very efficient protection in a small layout area. Since there is no diffusion or polysilicon resistor in the proposed ESD protection circuit, the RC delay between each I/O pad and its internal circuits is very low and the high-speed applications are feasible. The experimental results show that this full-SCR protection circuit can successfully perform very effective protection against ESD damages. Moreover, the proposed ESD protection circuit is fully process compatible with n-well or p-well CMOS and BiCMOS technologies.
|Journal||Electrical Overstress/Electrostatic Discharge Symposium Proceedings|
|State||Published - 1 Dec 1992|
|Event||Electrical Overstress/Electrostatic Discharge Symposium Proceedings - 1992 EOS/ESD - Dallas, TX, USA|
Duration: 16 Sep 1992 → 18 Sep 1992