Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection

Ming-Dou Ker; Hun Hsien Chang

doi:10.1109/CICC.1998.695036

Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection

Ming-Dou Ker^*, Hun Hsien Chang

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

2 Scopus citations

Abstract

A novel design has been proposed to safely apply the NCLSCR (NMOS-controlled lateral SCR) and PCLSCR (PMOS-controlled lateral SCR) devices for whole-chip ESD (electrostatic discharge) protection in CMOS IC's without causing the unexpected operation errors or the VDD-to-VSS latchup issue. By using the cascode configuration, the ESD protection circuit with the cascode NCLSCR's or PCLSCR's has a tunable holding voltage greater than VDD of the IC's. Such cascode NCLSCR's (or PCLSCR's) can provide the CMOS IC's with effective ESD protection but without accidentally triggering on by the overshooting (under-shooting) noise pulses in the system applications. This novel cascode NCLSCR's (PCLSCR's) design has been practically applied to protect the IC's in a 0.35-μm silicide CMOS technology with the HBM ESD robustness above 3KV.

Original language	English
Pages (from-to)	541-544
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.1998.695036
State	Published - 1 Jan 1998
Event	Proceedings of the 1998 IEEE Custom Integrated Circuits Conference - Santa Clara, CA, USA Duration: 11 May 1998 → 14 May 1998

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title = "Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection",

abstract = "A novel design has been proposed to safely apply the NCLSCR (NMOS-controlled lateral SCR) and PCLSCR (PMOS-controlled lateral SCR) devices for whole-chip ESD (electrostatic discharge) protection in CMOS IC's without causing the unexpected operation errors or the VDD-to-VSS latchup issue. By using the cascode configuration, the ESD protection circuit with the cascode NCLSCR's or PCLSCR's has a tunable holding voltage greater than VDD of the IC's. Such cascode NCLSCR's (or PCLSCR's) can provide the CMOS IC's with effective ESD protection but without accidentally triggering on by the overshooting (under-shooting) noise pulses in the system applications. This novel cascode NCLSCR's (PCLSCR's) design has been practically applied to protect the IC's in a 0.35-μm silicide CMOS technology with the HBM ESD robustness above 3KV.",

author = "Ming-Dou Ker and Chang, {Hun Hsien}",

year = "1998",

month = jan,

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doi = "10.1109/CICC.1998.695036",

language = "English",

pages = "541--544",

journal = "Proceedings of the Custom Integrated Circuits Conference",

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publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "null ; Conference date: 11-05-1998 Through 14-05-1998",

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AU - Ker, Ming-Dou

AU - Chang, Hun Hsien

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Y1 - 1998/1/1

N2 - A novel design has been proposed to safely apply the NCLSCR (NMOS-controlled lateral SCR) and PCLSCR (PMOS-controlled lateral SCR) devices for whole-chip ESD (electrostatic discharge) protection in CMOS IC's without causing the unexpected operation errors or the VDD-to-VSS latchup issue. By using the cascode configuration, the ESD protection circuit with the cascode NCLSCR's or PCLSCR's has a tunable holding voltage greater than VDD of the IC's. Such cascode NCLSCR's (or PCLSCR's) can provide the CMOS IC's with effective ESD protection but without accidentally triggering on by the overshooting (under-shooting) noise pulses in the system applications. This novel cascode NCLSCR's (PCLSCR's) design has been practically applied to protect the IC's in a 0.35-μm silicide CMOS technology with the HBM ESD robustness above 3KV.

AB - A novel design has been proposed to safely apply the NCLSCR (NMOS-controlled lateral SCR) and PCLSCR (PMOS-controlled lateral SCR) devices for whole-chip ESD (electrostatic discharge) protection in CMOS IC's without causing the unexpected operation errors or the VDD-to-VSS latchup issue. By using the cascode configuration, the ESD protection circuit with the cascode NCLSCR's or PCLSCR's has a tunable holding voltage greater than VDD of the IC's. Such cascode NCLSCR's (or PCLSCR's) can provide the CMOS IC's with effective ESD protection but without accidentally triggering on by the overshooting (under-shooting) noise pulses in the system applications. This novel cascode NCLSCR's (PCLSCR's) design has been practically applied to protect the IC's in a 0.35-μm silicide CMOS technology with the HBM ESD robustness above 3KV.

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JF - Proceedings of the Custom Integrated Circuits Conference

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Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection

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