Novel bipolar transistor isolation structure using combined selective epitaxial growth and planarization technique

J. N. Burghartz*, J. Wamock, J. D. Cressler, C. L. Stanis, R. C. McIntosh, J. Y.C. Sun, J. H. Comfort, J. M.C. Stork, K. A. Jenkins, E. F. Crabbé, W. Lee, M. Gilbert

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A novel bipolar isolation structure with capability of significantly reducing collector-base capacitance and base resistance is presented. A silicon-on-insulator (SOI) region surrounding the collector opening is used to minimize the collector window width, and to increase the thickness of the extrinsic base contact layer for a given device topography. This partial-SOI isolation structure can be combined with any type of emitter-base self-alined bipolar transistor structure.

Original languageEnglish
Title of host publicationEuropean Solid-State Device Research Conference
EditorsHerman E. Maes, Roger J. Van Overstraeten, Robert P. Mertens
PublisherIEEE Computer Society
Pages531-534
Number of pages4
ISBN (Electronic)0444894780
StatePublished - 1992
Event22nd European Solid State Device Research Conference, ESSDERC 1992 - Leuven, Belgium
Duration: 14 Sep 199217 Sep 1992

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Conference

Conference22nd European Solid State Device Research Conference, ESSDERC 1992
Country/TerritoryBelgium
CityLeuven
Period14/09/9217/09/92

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