Nonvolatile memory characteristics with embedded hemispherical silicon nanocrystals

Jian Hao Chen; Tan Fu Lei; Dolf Landheer; Xiaohua Wu; Ming Wen Ma; Woei Cherng Wu; Tsung Yu Yang; Tien-Sheng Chao

doi:10.1143/JJAP.46.6586

Nonvolatile memory characteristics with embedded hemispherical silicon nanocrystals

Jian Hao Chen^*, Tan Fu Lei, Dolf Landheer, Xiaohua Wu, Ming Wen Ma, Woei Cherng Wu, Tsung Yu Yang, Tien-Sheng Chao

^*Corresponding author for this work

Department of Electrophysics

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

Silicon nanocrystal-embedded memories were fabricated by using the thermal agglomeration of an ultrathin (1.5-1.8nm) amorphous silicon (a-Si) film. The a-Si was deposited on a 4-nm tunnel-oxide layer by electron beam evaporation and subsequently annealed in situ at 850°C for 5 min. Hemispherical Si nanocrystals were self-assembled, and nonvolatile memories were fabricated after depositing a 17-nm control-oxide layer. A threshold voltage window of 0.9 V was achieved under write/erase (W/E) voltages of ±10 V, and good endurance characteristics up to 10⁴ cycles were exhibited. Increasing W/E voltages created a large memory window (>2.7V), and the retention characteristics showed little temperature dependence up to 85°C.

Original language	English
Pages (from-to)	6586-6588
Number of pages	3
Journal	Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume	46
Issue number	10 A
DOIs	https://doi.org/10.1143/JJAP.46.6586
State	Published - 9 Oct 2007

Keywords

Floating gate
Hemispherically shaped silicon
MOSFET
Nonvolatile memory
Silicon nanocrystal

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@article{329798d1794441788af541de04ee62eb,

title = "Nonvolatile memory characteristics with embedded hemispherical silicon nanocrystals",

abstract = "Silicon nanocrystal-embedded memories were fabricated by using the thermal agglomeration of an ultrathin (1.5-1.8nm) amorphous silicon (a-Si) film. The a-Si was deposited on a 4-nm tunnel-oxide layer by electron beam evaporation and subsequently annealed in situ at 850°C for 5 min. Hemispherical Si nanocrystals were self-assembled, and nonvolatile memories were fabricated after depositing a 17-nm control-oxide layer. A threshold voltage window of 0.9 V was achieved under write/erase (W/E) voltages of ±10 V, and good endurance characteristics up to 104 cycles were exhibited. Increasing W/E voltages created a large memory window (>2.7V), and the retention characteristics showed little temperature dependence up to 85°C.",

keywords = "Floating gate, Hemispherically shaped silicon, MOSFET, Nonvolatile memory, Silicon nanocrystal",

author = "Chen, {Jian Hao} and Lei, {Tan Fu} and Dolf Landheer and Xiaohua Wu and Ma, {Ming Wen} and Wu, {Woei Cherng} and Yang, {Tsung Yu} and Tien-Sheng Chao",

year = "2007",

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doi = "10.1143/JJAP.46.6586",

language = "English",

volume = "46",

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journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers",

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T1 - Nonvolatile memory characteristics with embedded hemispherical silicon nanocrystals

AU - Chen, Jian Hao

AU - Lei, Tan Fu

AU - Landheer, Dolf

AU - Wu, Xiaohua

AU - Ma, Ming Wen

AU - Wu, Woei Cherng

AU - Yang, Tsung Yu

AU - Chao, Tien-Sheng

PY - 2007/10/9

Y1 - 2007/10/9

N2 - Silicon nanocrystal-embedded memories were fabricated by using the thermal agglomeration of an ultrathin (1.5-1.8nm) amorphous silicon (a-Si) film. The a-Si was deposited on a 4-nm tunnel-oxide layer by electron beam evaporation and subsequently annealed in situ at 850°C for 5 min. Hemispherical Si nanocrystals were self-assembled, and nonvolatile memories were fabricated after depositing a 17-nm control-oxide layer. A threshold voltage window of 0.9 V was achieved under write/erase (W/E) voltages of ±10 V, and good endurance characteristics up to 104 cycles were exhibited. Increasing W/E voltages created a large memory window (>2.7V), and the retention characteristics showed little temperature dependence up to 85°C.

AB - Silicon nanocrystal-embedded memories were fabricated by using the thermal agglomeration of an ultrathin (1.5-1.8nm) amorphous silicon (a-Si) film. The a-Si was deposited on a 4-nm tunnel-oxide layer by electron beam evaporation and subsequently annealed in situ at 850°C for 5 min. Hemispherical Si nanocrystals were self-assembled, and nonvolatile memories were fabricated after depositing a 17-nm control-oxide layer. A threshold voltage window of 0.9 V was achieved under write/erase (W/E) voltages of ±10 V, and good endurance characteristics up to 104 cycles were exhibited. Increasing W/E voltages created a large memory window (>2.7V), and the retention characteristics showed little temperature dependence up to 85°C.

KW - Floating gate

KW - Hemispherically shaped silicon

KW - MOSFET

KW - Nonvolatile memory

KW - Silicon nanocrystal

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U2 - 10.1143/JJAP.46.6586

DO - 10.1143/JJAP.46.6586

M3 - Article

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SN - 0021-4922

VL - 46

SP - 6586

EP - 6588

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

IS - 10 A

ER -

Nonvolatile memory characteristics with embedded hemispherical silicon nanocrystals

Abstract

Keywords

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