New VLSI architecture without global broadcast for 2-D digital filters

Lan-Da Van; Chih Chun Tang; Shing Tenqchen; Wu Shiung Feng

doi:10.1109/ISCAS.2000.857153

New VLSI architecture without global broadcast for 2-D digital filters

Lan-Da Van^*, Chih Chun Tang, Shing Tenqchen, Wu Shiung Feng

^*Corresponding author for this work

Institute of Computer Science and Engineering

Research output: Contribution to journal › Conference article › peer-review

6 Scopus citations

Abstract

In this paper, we propose the new two-dimensional (2-D) systolic-array structures of IIR/FIR digital filters without global broadcast by the different derivation and another systolic transformation. For more practical considerations, we further provide a detailed block diagram of a 2-D FIR filter using recently proposed multiplier to reduce the roundoff quantization error in the logic-gate level. These proposed systolic structures amenable to VLSI implementation permit the 2-D input sequence to be scanned in row-wise mode and locally broadcast one value each clock per delay element.

Original language	English
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	1
DOIs	https://doi.org/10.1109/ISCAS.2000.857153
State	Published - 1 Jan 2000
Event	Proceedings of the IEEE 2000 International Symposium on Circuits and Systems - Geneva, Switz Duration: 28 May 2000 → 31 May 2000

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abstract = "In this paper, we propose the new two-dimensional (2-D) systolic-array structures of IIR/FIR digital filters without global broadcast by the different derivation and another systolic transformation. For more practical considerations, we further provide a detailed block diagram of a 2-D FIR filter using recently proposed multiplier to reduce the roundoff quantization error in the logic-gate level. These proposed systolic structures amenable to VLSI implementation permit the 2-D input sequence to be scanned in row-wise mode and locally broadcast one value each clock per delay element.",

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AU - Van, Lan-Da

AU - Tang, Chih Chun

AU - Tenqchen, Shing

AU - Feng, Wu Shiung

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N2 - In this paper, we propose the new two-dimensional (2-D) systolic-array structures of IIR/FIR digital filters without global broadcast by the different derivation and another systolic transformation. For more practical considerations, we further provide a detailed block diagram of a 2-D FIR filter using recently proposed multiplier to reduce the roundoff quantization error in the logic-gate level. These proposed systolic structures amenable to VLSI implementation permit the 2-D input sequence to be scanned in row-wise mode and locally broadcast one value each clock per delay element.

AB - In this paper, we propose the new two-dimensional (2-D) systolic-array structures of IIR/FIR digital filters without global broadcast by the different derivation and another systolic transformation. For more practical considerations, we further provide a detailed block diagram of a 2-D FIR filter using recently proposed multiplier to reduce the roundoff quantization error in the logic-gate level. These proposed systolic structures amenable to VLSI implementation permit the 2-D input sequence to be scanned in row-wise mode and locally broadcast one value each clock per delay element.

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M3 - Conference article

AN - SCOPUS:0033719818

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VL - 1

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - Proceedings of the IEEE 2000 International Symposium on Circuits and Systems

Y2 - 28 May 2000 through 31 May 2000

ER -

New VLSI architecture without global broadcast for 2-D digital filters

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