New transient detection circuit for system-level ESD protection

Cheng Cheng Yen; Chi Sheng Liao; Ming-Dou Ker

doi:10.1109/VDAT.2008.4542442

New transient detection circuit for system-level ESD protection

Cheng Cheng Yen^*, Chi Sheng Liao, Ming-Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit can be co-designed to fix the system-level ESD issues. The circuit performance to detect different positive and negative ESD-induced fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.18-μm CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping.

Original language	English
Title of host publication	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Pages	180-183
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2008.4542442
State	Published - 5 Sep 2008
Event	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT - Hsinchu, Taiwan Duration: 23 Apr 2008 → 25 Apr 2008

Publication series

Name	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Conference

Conference	2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT
Country/Territory	Taiwan
City	Hsinchu
Period	23/04/08 → 25/04/08

Access to Document

10.1109/VDAT.2008.4542442

Cite this

@inproceedings{602ac7eaf3354a1383846da1ed6c918a,

title = "New transient detection circuit for system-level ESD protection",

abstract = "A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit can be co-designed to fix the system-level ESD issues. The circuit performance to detect different positive and negative ESD-induced fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.18-μm CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping.",

author = "Yen, {Cheng Cheng} and Liao, {Chi Sheng} and Ming-Dou Ker",

year = "2008",

month = sep,

day = "5",

doi = "10.1109/VDAT.2008.4542442",

language = "English",

isbn = "9781424416172",

series = "2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT",

pages = "180--183",

booktitle = "2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT",

note = "2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT ; Conference date: 23-04-2008 Through 25-04-2008",

}

Yen, CC, Liao, CS & Ker, M-D 2008, New transient detection circuit for system-level ESD protection. in 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT., 4542442, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT, pp. 180-183, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT, Hsinchu, Taiwan, 23/04/08. https://doi.org/10.1109/VDAT.2008.4542442

New transient detection circuit for system-level ESD protection. / Yen, Cheng Cheng; Liao, Chi Sheng; Ker, Ming-Dou.
2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. 2008. p. 180-183 4542442 (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - New transient detection circuit for system-level ESD protection

AU - Yen, Cheng Cheng

AU - Liao, Chi Sheng

AU - Ker, Ming-Dou

PY - 2008/9/5

Y1 - 2008/9/5

N2 - A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit can be co-designed to fix the system-level ESD issues. The circuit performance to detect different positive and negative ESD-induced fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.18-μm CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping.

AB - A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. By including this new proposed on-chip transient detection circuit, a hardware/firmware solution cooperated with power-on reset circuit can be co-designed to fix the system-level ESD issues. The circuit performance to detect different positive and negative ESD-induced fast electrical transients has been investigated by HSPICE simulator and verified in silicon chip. The experimental results in a 0.18-μm CMOS process have confirmed that the proposed on-chip transient detection circuit can detect fast electrical transients during system-level ESD zapping.

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U2 - 10.1109/VDAT.2008.4542442

DO - 10.1109/VDAT.2008.4542442

M3 - Conference contribution

AN - SCOPUS:50649113294

SN - 9781424416172

T3 - 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

SP - 180

EP - 183

BT - 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

T2 - 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT

Y2 - 23 April 2008 through 25 April 2008

ER -

New transient detection circuit for system-level ESD protection

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