Abstract
A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18- μm complementary- metaloxidesemiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.
Original language | English |
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Article number | 5406116 |
Pages (from-to) | 3533-3543 |
Number of pages | 11 |
Journal | IEEE Transactions on Industrial Electronics |
Volume | 57 |
Issue number | 10 |
DOIs | |
State | Published - 1 Oct 2010 |
Keywords
- Electrical-fast-transient (EFT) test
- electromagnetic compatibility
- electrostatic discharge (ESD)
- system-level ESD test
- transient detection circuit