New transient detection circuit for on-chip protection design against system-level electrical-transient disturbance

Ming-Dou Ker; Cheng Cheng Yen

doi:10.1109/TIE.2009.2039456

New transient detection circuit for on-chip protection design against system-level electrical-transient disturbance

Ming-Dou Ker^*, Cheng Cheng Yen

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

19 Scopus citations

Abstract

A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18- μm complementary- metaloxidesemiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.

Original language	English
Article number	5406116
Pages (from-to)	3533-3543
Number of pages	11
Journal	IEEE Transactions on Industrial Electronics
Volume	57
Issue number	10
DOIs	https://doi.org/10.1109/TIE.2009.2039456
State	Published - 1 Oct 2010

Keywords

Electrical-fast-transient (EFT) test
electromagnetic compatibility
electrostatic discharge (ESD)
system-level ESD test
transient detection circuit

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10.1109/TIE.2009.2039456

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title = "New transient detection circuit for on-chip protection design against system-level electrical-transient disturbance",

abstract = "A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18- μm complementary- metaloxidesemiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.",

keywords = "Electrical-fast-transient (EFT) test, electromagnetic compatibility, electrostatic discharge (ESD), system-level ESD test, transient detection circuit",

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AB - A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18- μm complementary- metaloxidesemiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.

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KW - electromagnetic compatibility

KW - electrostatic discharge (ESD)

KW - system-level ESD test

KW - transient detection circuit

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New transient detection circuit for on-chip protection design against system-level electrical-transient disturbance

Abstract

Keywords

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