Abstract
We propose a new efficient serial architecture to implement the Berlekamp-Massey algorithm, which is frequently used in BCH and Reed-Solomon decoders. An inversionless Berlekamp-Massey algorithm is adopted which not only eliminates the finite-field inverter but also introduces additional parallelism. We discover a clever scheduling of three finite-field multipliers to implement the algorithm very efficiently. Compared to a previously proposed serial Berlekamp-Massey architecture, our technique significantly reduces the latency.
Original language | English |
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Pages (from-to) | 481-483 |
Number of pages | 3 |
Journal | IEEE Transactions on Communications |
Volume | 47 |
Issue number | 4 |
DOIs | |
State | Published - 1 Jan 1999 |