New low-leakage power-rail ESD clamp circuit in a 65-nm low-voltage CMOS process

Ming-Dou Ker*, Po Yen Chiu

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    12 Scopus citations

    Abstract

    A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with consideration of the gate leakage issue has been proposed and verified in a 65-nm low-voltage CMOS process. Consisting of the new low-leakage ESD-detection circuit and the ESD clamp device of a substrate-triggered silicon-controlled rectifier, the new proposed power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has a very low leakage current of only 116 nA at room temperature (25 °C) under the power-supply voltage of 1 V. Moreover, the new proposed power-rail ESD clamp circuit can achieve ESD robustness of over 8 kV, 800 V, and over 2 kV in human-body-model, machine-model, and charged-device-model ESD tests, respectively.

    Original languageEnglish
    Article number5549874
    Pages (from-to)474-483
    Number of pages10
    JournalIEEE Transactions on Device and Materials Reliability
    Volume11
    Issue number3
    DOIs
    StatePublished - 1 Sep 2011

    Keywords

    • Electrostatic discharge (ESD)
    • gate leakage
    • power-rail ESD clamp circuit
    • substrate-triggered silicon-controlled rectifier (STSCR)

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