Three new device structures to effectively reduce the layout area of CMOS output buffers with higher driving capability and better ESD reliability are proposed. With theoretical calculation and experimental verification, both the higher output driving/sinking capability and the stronger ESD robustness of CMOS output buffers can be practically achieved by the new proposed layout designs within smaller layout area. The output devices assembled by a plurality of the proposed basic layout cells have a lower ploy-gate resistance and a smaller drain capacitance than that by the traditional finger-type layout.
|Number of pages
|Published - 1 Dec 1997
|Proceedings of the 1997 6th International Symposium on the Physical & Failure Analysis of Integrated Circuits, IPFA - Singapore, Singapore
Duration: 21 Jul 1997 → 25 Jul 1997
|Proceedings of the 1997 6th International Symposium on the Physical & Failure Analysis of Integrated Circuits, IPFA
|21/07/97 → 25/07/97