New gate-bias voltage-generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process

Jung Sheng Chen; Ming-Dou Ker

doi:10.1109/JDT.2007.900916

New gate-bias voltage-generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process

Jung Sheng Chen^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

3 Scopus citations

Abstract

A new proposed gate-bias voltage-generating technique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) is proposed. The new proposed gate-bias voltage-generating circuit with threshold-voltage compensation has been successfully verified in an 8-μm LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5% under a biasing voltage of 3 V. The new proposed gate-bias voltage-generating technique with threshold-voltage compensation enables the analog circuits to be integrated and implemented by the LTPS process on glass substrate for an active matrix LCD panel.

Original language	English
Pages (from-to)	309-314
Number of pages	6
Journal	IEEE/OSA Journal of Display Technology
Volume	3
Issue number	3
DOIs	https://doi.org/10.1109/JDT.2007.900916
State	Published - 1 Sep 2007

Keywords

Analog circuit
Biasing circuit
Low-temperature polycrystalline silicon (LTPS)
Thin-film transistor (TFT)
Threshold-voltage compensation
Threshold-voltage variation

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10.1109/JDT.2007.900916

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@article{38d6d6cde90e4171962315e6d67bcffa,

title = "New gate-bias voltage-generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process",

abstract = "A new proposed gate-bias voltage-generating technique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) is proposed. The new proposed gate-bias voltage-generating circuit with threshold-voltage compensation has been successfully verified in an 8-μm LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5% under a biasing voltage of 3 V. The new proposed gate-bias voltage-generating technique with threshold-voltage compensation enables the analog circuits to be integrated and implemented by the LTPS process on glass substrate for an active matrix LCD panel.",

keywords = "Analog circuit, Biasing circuit, Low-temperature polycrystalline silicon (LTPS), Thin-film transistor (TFT), Threshold-voltage compensation, Threshold-voltage variation",

author = "Chen, {Jung Sheng} and Ming-Dou Ker",

year = "2007",

month = sep,

day = "1",

doi = "10.1109/JDT.2007.900916",

language = "English",

volume = "3",

pages = "309--314",

journal = "IEEE/OSA Journal of Display Technology",

issn = "1551-319X",

publisher = "IEEE Computer Society",

number = "3",

}

TY - JOUR

T1 - New gate-bias voltage-generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process

AU - Chen, Jung Sheng

AU - Ker, Ming-Dou

PY - 2007/9/1

Y1 - 2007/9/1

N2 - A new proposed gate-bias voltage-generating technique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) is proposed. The new proposed gate-bias voltage-generating circuit with threshold-voltage compensation has been successfully verified in an 8-μm LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5% under a biasing voltage of 3 V. The new proposed gate-bias voltage-generating technique with threshold-voltage compensation enables the analog circuits to be integrated and implemented by the LTPS process on glass substrate for an active matrix LCD panel.

AB - A new proposed gate-bias voltage-generating technique with threshold-voltage compensation for analog circuits in the low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) is proposed. The new proposed gate-bias voltage-generating circuit with threshold-voltage compensation has been successfully verified in an 8-μm LTPS process. The experimental results have shown that the impact of TFT threshold-voltage variation on the biasing circuit can be reduced from 30% to 5% under a biasing voltage of 3 V. The new proposed gate-bias voltage-generating technique with threshold-voltage compensation enables the analog circuits to be integrated and implemented by the LTPS process on glass substrate for an active matrix LCD panel.

KW - Analog circuit

KW - Biasing circuit

KW - Low-temperature polycrystalline silicon (LTPS)

KW - Thin-film transistor (TFT)

KW - Threshold-voltage compensation

KW - Threshold-voltage variation

UR - http://www.scopus.com/inward/record.url?scp=34548090274&partnerID=8YFLogxK

U2 - 10.1109/JDT.2007.900916

DO - 10.1109/JDT.2007.900916

M3 - Article

AN - SCOPUS:34548090274

SN - 1551-319X

VL - 3

SP - 309

EP - 314

JO - IEEE/OSA Journal of Display Technology

JF - IEEE/OSA Journal of Display Technology

IS - 3

ER -

New gate-bias voltage-generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process

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