New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process

Chih Ting Yeh*, Ming-Dou Ker

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

    3 Scopus citations

    Fingerprint

    Dive into the research topics of 'New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process'. Together they form a unique fingerprint.

    Engineering & Materials Science