New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process

Chih Ting Yeh; Ming-Dou Ker

doi:10.1109/VLSI-DAT.2012.6212606

New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process

Chih Ting Yeh^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

A 2VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit with only thin gate oxide 1V devices and silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. The proposed power-rail ESD clamp circuit has an ultra-low standby leakage current by reducing the voltage drop across the gate oxide of the devices in the ESD detection circuit. From the measured results, the proposed design with SCR dimension of 50m in width can achieve 6.5kV human-body-model (HBM), 300V machine-model (MM) ESD levels, and an ultra-low standby leakage current of 34.1nA at room temperature under the normal circuit operating condition with 1.8V bias.

Original language	English
Title of host publication	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers
DOIs	https://doi.org/10.1109/VLSI-DAT.2012.6212606
State	Published - 25 Jul 2012
Event	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Hsinchu, Taiwan Duration: 23 Apr 2012 → 25 Apr 2012

Publication series

Name	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

Conference

Conference	2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012
Country/Territory	Taiwan
City	Hsinchu
Period	23/04/12 → 25/04/12

Access to Document

10.1109/VLSI-DAT.2012.6212606

Cite this

Yeh, C. T., & Ker, M-D. (2012). New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers [6212606] (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). https://doi.org/10.1109/VLSI-DAT.2012.6212606

Yeh, Chih Ting ; Ker, Ming-Dou. / New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

@inproceedings{fa2383961c9448e0a190cc4660ccfca5,

title = "New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process",

abstract = "A 2VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit with only thin gate oxide 1V devices and silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. The proposed power-rail ESD clamp circuit has an ultra-low standby leakage current by reducing the voltage drop across the gate oxide of the devices in the ESD detection circuit. From the measured results, the proposed design with SCR dimension of 50m in width can achieve 6.5kV human-body-model (HBM), 300V machine-model (MM) ESD levels, and an ultra-low standby leakage current of 34.1nA at room temperature under the normal circuit operating condition with 1.8V bias.",

author = "Yeh, {Chih Ting} and Ming-Dou Ker",

year = "2012",

month = jul,

day = "25",

doi = "10.1109/VLSI-DAT.2012.6212606",

language = "English",

isbn = "9781457720819",

series = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers",

booktitle = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers",

note = "2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 ; Conference date: 23-04-2012 Through 25-04-2012",

}

Yeh, CT & Ker, M-D 2012, New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. in 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers., 6212606, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers, 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, 23/04/12. https://doi.org/10.1109/VLSI-DAT.2012.6212606

New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. / Yeh, Chih Ting; Ker, Ming-Dou.
2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212606 (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process

AU - Yeh, Chih Ting

AU - Ker, Ming-Dou

PY - 2012/7/25

Y1 - 2012/7/25

N2 - A 2VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit with only thin gate oxide 1V devices and silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. The proposed power-rail ESD clamp circuit has an ultra-low standby leakage current by reducing the voltage drop across the gate oxide of the devices in the ESD detection circuit. From the measured results, the proposed design with SCR dimension of 50m in width can achieve 6.5kV human-body-model (HBM), 300V machine-model (MM) ESD levels, and an ultra-low standby leakage current of 34.1nA at room temperature under the normal circuit operating condition with 1.8V bias.

AB - A 2VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit with only thin gate oxide 1V devices and silicon-controlled rectifier (SCR) as main ESD clamp device has been proposed and verified in a 65nm CMOS process. The proposed power-rail ESD clamp circuit has an ultra-low standby leakage current by reducing the voltage drop across the gate oxide of the devices in the ESD detection circuit. From the measured results, the proposed design with SCR dimension of 50m in width can achieve 6.5kV human-body-model (HBM), 300V machine-model (MM) ESD levels, and an ultra-low standby leakage current of 34.1nA at room temperature under the normal circuit operating condition with 1.8V bias.

UR - http://www.scopus.com/inward/record.url?scp=84864075457&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT.2012.6212606

DO - 10.1109/VLSI-DAT.2012.6212606

M3 - Conference contribution

AN - SCOPUS:84864075457

SN - 9781457720819

T3 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

BT - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers

T2 - 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012

Y2 - 23 April 2012 through 25 April 2012

ER -

Yeh CT, Ker M-D. New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. In 2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers. 2012. 6212606. (2012 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2012 - Proceedings of Technical Papers). doi: 10.1109/VLSI-DAT.2012.6212606

New design on 2VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this