Nearly Ideal Subthreshold Swing in Monolayer MoS Top-Gate nFETs with Scaled EOT of 1 nm

Tsung En Lee*, Yuan Chun Su, Bo Jiun Lin, Yi Xuan Chen, Wei Sheng Yun, Po Hsun Ho, Jer Fu Wang, Sheng Kai Su, Chen Feng Hsu, Po Sen Mao, Yu Cheng Chang, Chao Hsin Chien, Bo Heng Liu, Chien Ying Su, Chi Chung Kei, Han Wang, H. S. Philip Wong, T. Y. Lee, Wen Hao Chang, Chao Ching ChengIuliana P. Radu

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Transistor scaling enabled by gate length scaling requires EOT scaling to less than 1 nm thickness [1]. This work successfully integrates Hf-based ALD higher-k dielectrics with CVD-grown monolayer (1L) MoS2 to build top-gate nFET with EOT 1 nm with nearly ideal subthreshold swing of 68 mV/dec. The gate stack described here achieves a high varepsilon-{ mathrm{e} mathrm{f} mathrm{f}} 13.53, a large mathrm{E}-{ mathrm{B} mathrm{D}} 12.4MV/cm, and excellent leakage current density. This is a remarkable performance among reported gate dielectrics on the transition metal dichalcogenides (TMDs) on which it is notoriously difficult to deposit a pinhole-free dielectric.

Original languageEnglish
Title of host publication2022 International Electron Devices Meeting, IEDM 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages741-744
Number of pages4
ISBN (Electronic)9781665489591
DOIs
StatePublished - 2022
Event2022 International Electron Devices Meeting, IEDM 2022 - San Francisco, United States
Duration: 3 Dec 20227 Dec 2022

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2022-December
ISSN (Print)0163-1918

Conference

Conference2022 International Electron Devices Meeting, IEDM 2022
Country/TerritoryUnited States
CitySan Francisco
Period3/12/227/12/22

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