@inproceedings{b7bd3cdad9d04faea2c2409d8870a1a4,
title = "NBL Causing Low Latch-up Immunity between HV-PMOS and LV-P/NMOS in a 0.15-μm BCD Process",
abstract = "The N-buried layer (NBL) causing low latch-up immunity between the HV-PMOS and LV-PMOS / LV-NMOS is studied in this work. The NBL layer has been often used to isolate the circuits from the common p-substrate for operating at different voltages, or to avoid noise coupling through the common p-substrate. As the HV circuits and LV circuits integrated together on the same silicon chip, the parasitic latchup paths between them would be easily triggered into a latch-up state under the current-trigger latch-up test. The latch-up or latch-up-like issues between the neighbor circuits with different power domains surrounding by NBL must be paid attention. ",
author = "Chen, {Chao Yang} and Lee, {Jian Hsing} and Karuna Nidhi and Bin, {Tzer Yaa} and Lin, {Geeng Lih} and Ming-Dou Ker",
note = "Publisher Copyright: {\textcopyright} 2021 EOS/ESD Association, Inc.; 43rd Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2021 ; Conference date: 26-09-2021 Through 01-10-2021",
year = "2021",
month = sep,
day = "26",
doi = "10.23919/EOS/ESD52038.2021.9574756",
language = "English",
series = "Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2021, EOS/ESD 2021",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2021, EOS/ESD 2021",
address = "美國",
}