NBL Causing Low Latch-up Immunity between HV-PMOS and LV-P/NMOS in a 0.15-μm BCD Process

Chao Yang Chen, Jian Hsing Lee, Karuna Nidhi, Tzer Yaa Bin, Geeng Lih Lin, Ming-Dou Ker

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

The N-buried layer (NBL) causing low latch-up immunity between the HV-PMOS and LV-PMOS / LV-NMOS is studied in this work. The NBL layer has been often used to isolate the circuits from the common p-substrate for operating at different voltages, or to avoid noise coupling through the common p-substrate. As the HV circuits and LV circuits integrated together on the same silicon chip, the parasitic latchup paths between them would be easily triggered into a latch-up state under the current-trigger latch-up test. The latch-up or latch-up-like issues between the neighbor circuits with different power domains surrounding by NBL must be paid attention.

Original languageEnglish
Title of host publicationElectrical Overstress/Electrostatic Discharge Symposium Proceedings 2021, EOS/ESD 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)158537329X, 9781585373291
DOIs
StatePublished - 26 Sep 2021
Event43rd Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2021 - Tucson, United States
Duration: 26 Sep 20211 Oct 2021

Publication series

NameElectrical Overstress/Electrostatic Discharge Symposium Proceedings 2021, EOS/ESD 2021

Conference

Conference43rd Annual Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD 2021
Country/TerritoryUnited States
CityTucson
Period26/09/211/10/21

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